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Datasheet File OCR Text:

ZL50020 Enhanced 2 K Digital Switch
Data Sheet Features
* 2048 channel x 2048 channel non-blocking digital Time Division Multiplex (TDM) switch at 8.192 Mbps and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384 Mbps 32 serial TDM input, 32 serial TDM output streams Output streams can be configured as bidirectional for connection to backplanes Exceptional input clock cycle to cycle variation tolerance (20 ns for all rates) Per-stream input and output data rate conversion selection at 2.048, 4.096, 8.192 or 16.384 Mbps. Input and output data rates can differ Per-stream high impedance control outputs (STOHZ) for 16 output streams Per-stream input bit delay with flexible sampling point selection * * * * * * * Ordering Information ZL50020GAC 256-ball PBGA ZL50020QCC 256-lead LQFP -40C to +85C Per-stream output bit and fractional bit advancement Per-channel ITU-T G.711 PCM A-Law/-Law Translation Four frame pulse and four reference clock outputs Three programmable delayed frame pulse outputs Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz Input frame pulses:61 ns, 122 ns, 244 ns Per-channel constant or variable throughput delay for frame integrity and low latency applications
October 2004
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VDD_CORE
VDD_IO
VDD_COREA
VDD_IOA
VSS
RESET
ODE
STi[31:0] FPi CKi MODE_4M0 MODE_4M1
S/P Converter
Data Memory
P/S Converter
STio[31:0]
Input Timing
Connection Memory
Output HiZ Control
STOHZ[15:0]
Output Timing
FPo[3:0] CKo[3:0] FPo_OFF[2:0]
Internal Registers & Microprocessor Interface
Test Port
D[15:0]
DS_RD
A[13:0]
R/W_WR
Figure 1 - ZL50020 Functional Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
MOT_INTEL
DTA_RDY
TRST
TDi
TMS
TCK
TDo
CS
ZL50020
* * * * * * * * Per Stream (32) Bit Error Rate Test circuits complying to ITU-O.151 Per-channel high impedance output control Per-channel message mode Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses Connection memory block programming Supports ST-BUS and GCI-Bus standards for input and output timing IEEE-1149.1 (JTAG) test port 3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltage
Data Sheet
Applications
* * * * * * * PBX and IP-PBX Small and medium digital switching platforms Remote access servers and concentrators Wireless base stations and controllers Multi service access platforms Digital Loop Carriers Computer Telephony Integration
Description
The ZL50020 is a maximum 2048 x 2048 channel non-blocking digital Time Division Multiplex (TDM) switch. It has thirty-two input streams (STi0 - 31) and thirty-two output streams (STio0 - 31). The device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be independently programmed to operate at any of the following data rates: 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. The ZL50020 provides up to sixteen high impedance control outputs (STOHZ0 - 15) to support the use of external tristate drivers for the first sixteen output streams (STio0 - 15). The output streams can be configured to operate in bi-directional mode, in which case STi0 - 31 will be ignored. The device contains two types of internal memory - data memory and connection memory. There are four modes of operation - Connection Mode, Message Mode, BER mode and high impedance mode. In Connection Mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel (the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for the storage of microprocessor data. Using Zarlink's Message Mode capability, microprocessor data can be broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and status information for external circuits or other TDM devices. In BER mode the output channel data is replaced with a pseudorandom bit sequence (PRBS) from one of 32 PRBS generators that generates a 215-1 pattern. On the input side channels can be routed to one of 32 bit error detectors. In high impedance mode the selected output channel can be put into a high impedance state. The configurable non-multiplexed microprocessor port allows users to program various device operating modes and switching configurations. Users can employ the microprocessor port to perform register read/write, connection memory read/write, and data memory read operations. The port is configurable to interface with either Motorola or Intel-type microprocessors. The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
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Zarlink Semiconductor Inc.
ZL50020 Table of Contents
Data Sheet
1.0 Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 BGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 QFP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.0 Data Rates and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 Input Clock (CKi) and Input Frame Pulse (FPi) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.0 ST-BUS and GCI-Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.0 Output Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.0 Data Input Delay and Data Output Advancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.1 Input Bit Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.2 Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.3 Output Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.4 Fractional Output Bit Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.5 External High Impedance Control Advancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.1 Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2 Constant Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.0 Connection Memory Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.0 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.1 Memory Block Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 12.0 Device Performance Divided Clock and Multiplied Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 12.1 Divided Clock Mode Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 12.2 Multiplied Clock Mode Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 13.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.0 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.1 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.2 Device Initialization on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 15.0 Pseudo Random Bit Generation and Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 16.0 PCM A-law/m-law Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 17.0 Quadrant Frame Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 18.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 18.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 18.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 18.3 Test Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 18.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 19.0 Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 20.0 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 21.0 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 21.1 Memory Address Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 21.2 Connection Memory Low (CM_L) Bit Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 21.3 Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 22.0 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 23.0 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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Zarlink Semiconductor Inc.
ZL50020 List of Figures
Data Sheet
Figure 1 - ZL50020 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50020 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package) . . . . . . . . . . . . . . . . . . . 7 Figure 3 - ZL50020 256-Lead 28 mm x 28 mm LQFP (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4 - Input Timing when CKIN1 - 0 bits = "10" in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5 - Input Timing when CKIN1 - 0 bits = "01" in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6 - Input Timing when CKIN1 - 0 = "00" in the CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7 - Output Timing for CKo0 and FPo0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 8 - Output Timing for CKo1 and FPo1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9 - Output Timing for CKo2 and FPo2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 10 - Output Timing for CKo3 and FPo3 with CK0FPo3SEL1-0="11" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 11 - Input Bit Delay Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 12 - Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 13 - Input Bit Delay and Factional Sampling Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14 - Output Bit Advancement Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 15 - Output Fractional Bit Advancement Timing Diagram (ST-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 16 - Channel Switching External High Impedance Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 17 - Data Throughput Delay for Variable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 18 - Data Throughput Delay for Constant Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 19 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 20 - Motorola Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 21 - Motorola Non-Multiplexed Bus Timing - Write Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 22 - Intel Non-Multiplexed Bus Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 23 - Intel Non-Multiplexed Bus Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 24 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 25 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 26 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 27 - ST-BUS Input Timing Diagram when Operated at 2, 4, 8 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 28 - ST-BUS Input Timing Diagram when Operated at 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 29 - GCI-Bus Input Timing Diagram when Operated at 2, 4, 8 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 30 - GCI-Bus Input Timing Diagram when Operated at 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 31 - ST-BUS Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 32 - GCI-Bus Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 33 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 34 - Output Drive Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 35 - Input and Output Frame Boundary Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 36 - FPo0 and CKo0 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 37 - FPo1 and CKo1 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 38 - FPo2 and CKo2 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 39 - FPo3 and CKo3 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 40 - Output Timing (ST-BUS Format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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Zarlink Semiconductor Inc.
ZL50020 List of Tables
Data Sheet
Table 1 - CKi and FPi Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2 - CKi and FPi Configurations for Divided Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3 - CKi and FPi Configurations for Multiplied Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4 - Output Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5 - Delay for Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 6 - Connection Memory Low After Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 7 - Connection Memory High After Block Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 8 - ZL50020 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 9 - Generated Output Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 10 - Input and Output Voice and Data Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 11 - Definition of the Four Quadrant Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 12 - Quadrant Frame Bit Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 13 - Address Map for Registers (A13 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 14 - Control Register (CR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 15 - Internal Mode Selection Register (IMS) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 16 - Software Reset Register (SRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 17 - Output Clock and Frame Pulse Control Register (OCFCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 18 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 19 - FPo_OFF[n] Register (FPo_OFF[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 20 - Internal Flag Register (IFR) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 21 - BER Error Flag Register 0 (BERFR0) BIts - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 22 - BER Error Flag Register 1 (BERFR1) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 23 - BER Receiver Lock Register 0 (BERLR0) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 24 - BER Receiver Lock Register 1 (BERLR1) Bits - Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 25 - Stream Input Control Register 0 - 31 (SICR0 - 31) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 26 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 27 - Stream Output Control Register 0 - 31 (SOCR0 - 31) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 28 - BER Receiver Start Register [n] (BRSR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 29 - BER Receiver Length Register [n] (BRLR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 30 - BER Receiver Control Register [n] (BRCR[n]) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 31 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 32 - Address Map for Memory Locations (A13 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 33 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 34 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 35 - Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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Zarlink Semiconductor Inc.
ZL50020
1.0 Changes Summary
Item Figure 2, "ZL50020 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package) Figure 3, "ZL50020 256-Lead 28 mm x 28 mm LQFP (top view) * * * * 9 15 30 37 38 3.0, "Pin Description" 4.0, "Device Overview" 12.0, "Device Performance Divided Clock and Multiplied Clock Modes" 19.0, "Register Address Mapping" 20.0, "Detailed Register Description" * * * * * * Change
Data Sheet
Page 7
Re-labeled IC_OPEN to MODE_4M0 Location: Ball M14 Re-labeled IC_OPEN to MODE_4M1 Location: Ball R13 Re-labeled IC_OPEN to MODE_4M0 Location: Pin 46 Re-labeled IC_OPEN to MODE_4M1 Location: Pin 48 Added MODE_4M0 & MODE_4M1 descriptions Added reference to ZLAN-120 "Mid-Density Digital Digital Switches Timing Modes" Added Table 8 "Operating Modes" along with description of table Changed from R/W to R only Changed Bit 11 description Changed Bits 6-5 Description - Added MODE 4M0/1
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Zarlink Semiconductor Inc.
ZL50020
2.0
2.1
1
A
Data Sheet
Pinout Diagrams
BGA Pinout
2 STi29 STi10 STi9 STi11 STi14 STi15 RESET VSS VDD_IOA VSS VDD_ COREA NC NC NC NC STio28 2 3 STi28 STi5 VSS VDD_IO STi8 STi12 4 STi27 STi4 STi7 STi3 VDD_IO STi13 5 STi25 CKo2 STi6 STi2 VSS VDD_IO TDo NC VSS VDD_ COREA VDD_IO VSS STOHZ3 STio3 STOHZ2 STio30 5 6 STi26 STi0 STi1 NC VDD_ CORE VDD_ CORE VDD_IO VSS CKo3 VDD_IO VDD_ CORE VDD_ CORE D1 STOHZ1 D2 NC 6 7 STi24 CKo0 CKo1 NC NC VDD_ CORE VSS VSS VSS VSS VDD_ CORE VDD_ CORE D5 D3 D4 NC 7 8 NC NC NC NC NC VSS VSS VSS VSS VSS VSS D6 D7 D8 D9 NC 8 9 NC VDD_ COREA VSS NC NC VSS VSS VSS VSS VSS VSS D10 D11 D14 D12 NC 9 10 STio22 FPi IC_Open VSS NC VDD_ CORE VSS VSS VSS VSS VDD_ CORE VDD_ CORE D13 NC D15 NC 10 11 STio23 CKi IC_Open FPo_ OFF1 VDD_ CORE VDD_ CORE VDD_IO A7 A3 VDD_IO VDD_ CORE VDD_ CORE R/W _WR STio5 CS NC 11 12 STio21 13 STio20 14 NC 15 NC ODE STio15 STio14 FPo2 FPo_ OFF2 FPo0 A11 A6 A1 STio9 STio8 STOHZ5 STOHZ7 STio7 NC 15 16 VSS STio19 STio18 STio16 STio17
A
VSS STi31
B
IC_Open IC_Open IC_GND IC_Open IC_GND IC_GND VSS VDD_IO A12 A9 A4 IC_Open VDD_IO VSS DTA_ RDY STio13 VDD_IO IC A13 A10 A5 A0 STio10 MOT _INTEL STio4 VSS VDD_IO STio12 FPo3 FPo1 FPo_ OFF0 A8 A2 STio11 MODE_ 4M0 VDD_IO VSS STio6 NC 14
B
C STi30
C
D STi17
D
E
STi16 STi19
E
F
STOHZ15 F STOHZ14 G STOHZ12 H STOHZ13 J STOHZ11 K STOHZ10 L STOHZ9 M STOHZ8 NC NC VSS 16
N
G STi18 H STi21
IC_GND IC_Open VSS VDD_IOA TMS TRST TDi VDD_IO VSS STOHZ0 STio29 3 VDD_ COREA VSS VSS TCK D0 STio0 STio1 STio2 STio31 4
J
STi20 STi22 STi23
K
L
M STio25
N STio24
P STio26 R STio27
STOHZ4 STOHZ6 DS_RD NC 12 MODE_ 4M1 NC 13
P
R
T
VSS 1
T
Note: A1 corner identified by metallized marking. Note: Pinout is shown as viewed through top of package.
Figure 2 - ZL50020 256-Ball 17 mm x 17 mm PBGA (as viewed through top of package)
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Zarlink Semiconductor Inc.
ZL50020
2.2 QFP Pinout
Data Sheet
STi28 STi29 VDD_IO STi30 STi31 STi_8 VSS STi_9 STi_10 STi_11 STi_12 STi_13 STi_14 STi_15 VDD_IO IC_GND VSS IC_Open RESET TDo VDD_CORE VSS NC VSS VDD_COREA VSS NC VDD_IOA NC VSS VSS VDD_COREA NC VDD_IOA CKo3 VSS NC VSS VDD_COREA VSS VDD_CORE TMS VSS NC NC TCK TRST TDi VDD_IO VSS STi_16 STi_17 STi_18 STi_19 STi_20 STi_21 VDD_IO STi_22 VSS STi_23 STio_24 STio_25 STio_26
194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 256
192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
STi27 STi26 STi25 STi24 VSS STi_7 VDD_IO STi_6 STi_5 STi_4 STi_3 STi_2 STi_1 STi_0 VSS VDD_IO NC VSS CKo2 VDD_CORE CKo1 VSS CKo0 VDD_IO NC NC NC NC NC NC VSS NC VDD_IO NC VSS VDD_COREA VSS FPi CKi IC_Open IC_Open IC_Open IC_Open IC_Open IC_GND VSS VDD_CORE VSS IC_GND VDD_IO VSS ODE NC NC NC NC NC NC NC VDD_IO STio_23 STio_22 STio_21 STio_20
STio_27
STio_19 STio_18 STio_17 STio_16 STOHZ_15 VSS STOHZ_14 VDD_IO STOHZ_13 STOHZ_12 STio_15 STio_14 STio_13 STio_12 VSS VDD_IO FPo3 VSS FPo2 VDD_CORE FPo_OFF2 IC_GND FPo1 IC_Open FPo_OFF1 VSS FPo0 VDD_IO FPo_OFF0 A13 A12 VSS A11 VDD_CORE A10 A9 A8 A7 A6 A5 A4 A3 A2 VSS A1 VDD_CORE A0 VSS IC_Open VDD_IO STOHZ_11 STOHZ_10 STOHZ_9 STOHZ_8 STio_11 STio_10 STio_9 VSS STio_8 VDD_IO NC NC NC NC
STio_28 STio_29 STio_30 STio_31 VDD_IO STio_0 STio_1 VSS STio_2 STio_3 STOHZ_0 STOHZ_1 STOHZ_2 STOHZ_3 VDD_IO D0 VSS D1 VDD_CORE D2 VSS D3 D4 D5 D6 D7 D8 D9 VDD_IO D10 VSS D11 VDD_CORE D12 VSS D13 D14 D15 R/W_WR CS MOT_INTEL DS_RD NC DTA_RDY VDD_CORE MODE_4M0
Figure 3 - ZL50020 256-Lead 28 mm x 28 mm LQFP (top view)
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Zarlink Semiconductor Inc.
MODE_4M1
VSS STio_4 STio_5 STio_6 STio_7 STOHZ_4 STOHZ_5 VDD_IO STOHZ_6
VDD_IO
STOHZ_7
VSS
VSS NC NC NC NC
ZL50020
3.0 Pin Description
LQFP Pin Number 19, 33, 45, 83, 95, 109, 146, 173, 213, 233 217, 231, 157, 224 5, 15, 29, 49, 57, 69, 79, 101, 113, 121, 133, 143, 160, 169, 177, 186, 195, 207, 241, 249 220, 226 8, 17, 21, 31, 35, 47, 50, 60, 71, 81, 85, 97, 103, 111, 114, 123, 142, 145, 147, 156, 158, 162, 171, 175, 178, 188, 199, 209, 214, 216, 218, 222, 223, 228, 230, 232, 235, 242, 251
Data Sheet
PBGA Pin Number E6, E11, F6, F7, F10, F11, L6, L7, L10, L11, M6, M7, M10, M11 H4, K5, B9, L2 D3, D14, E4, E13, F5, F12, G6, G11, K6, K11, L5, L12, N3, N14
Pin Name VDD_CORE
Description Power Supply for the core logic: +1.8 V
VDD_COREA VDD_IO
Power Supply for analog circuitry: +1.8 V Power Supply for I/O: +3.3 V
J2, J3 A1, A16, C3, C9, C14, D10, E5, E12, F8, F9, G7, G8, G9, G10, H2, H3, H6, H7, H8, H9, H10, J4, J5, J7, J8, J9, J10, K2, K4, K7, K8, K9, K10, L8, L9, M5, M12, P3, P14, T1, T16
VDD_IOA VSS
Power Supply for the CKo5 and CKo3 outputs: +3.3 V Ground
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Zarlink Semiconductor Inc.
ZL50020
PBGA Pin Number K3 LQFP Pin Number 234 Pin Name TMS Description
Data Sheet
Test Mode Select (5 V-Tolerant Input with Internal Pull-up) JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up resistor when it is not driven. Test Clock (5 V-Tolerant Schmitt-Triggered Input with Internal Pull-up) Provides the clock to the JTAG test logic. Test Reset (5 V-Tolerant Input with Internal Pull-up) Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low during power-up to ensure that the device is in the normal functional mode. When JTAG is not being used, this pin should be pulled low during normal operation. Test Serial Data In (5 V-Tolerant Input with Internal Pull-up) JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up resistor when it is not driven. Test Serial Data Out (5 V-Tolerant Three-state Output) JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG is not enabled. Internal Test Mode (5 V-Tolerant Input with Internal Pull-down) These pins may be left unconnected.
L4
238
TCK
L3
239
TRST
M3
240
TDi
G5
212
TDo
B12, B13, C10, C11, F13, G4, K12, C12, G3, D12, B14, C13
80, 105, 150, 151, 152, 153, 210, 149 144, 107, 148, 208
IC_Open
IC_GND
Internal Test Mode Enable (5 V-Tolerant Input) These pins MUST be low.
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Zarlink Semiconductor Inc.
ZL50020
PBGA Pin Number A8, A9, A14, A15, E10, M2, N2, P2, P16, R2, R16, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, D9, E8, C8, E7, D6, H5, P10, E9, D8, B8, D7 LQFP Pin Number 61, 62, 63, 64, 65, 66, 67, 68, 134, 135, 136, 137, 138, 139, 140, 152, 215, 219, 225, 229, 236, 237159, 163, 165, 167, 176, 221, 43, 161, 164, 166, 168 46, 48 Pin Name NC Description No Connect These pins MUST be left unconnected.
Data Sheet
M14, R13
MODE_4M0, MODE_4M1
4M Input Clock Mode 0 to 1 (5 V-Tolerant Input with internal pull-down) These two pins should be tied together and are typically used to select CKi = 4.096 MHz operation. See Table 8, "ZL50020 Operating Modes" on page 31 for a detailed explanation. See Table 14, "Control Register (CR) Bits" on page 38 for CKi and FPi selection using the CKIN1 - 0 bits. ST-BUS/GCI-Bus Frame Pulse Outputs 0 to 3 (5 V-Tolerant Three-state Outputs) FPo0: 8 kHz frame pulse corresponding to the 4.096 MHz output clock of CKo0. FPo1: 8 kHz frame pulse corresponding to the 8.192 MHz output clock of CKo1. FPo2: 8 kHz frame pulse corresponding to 16.384 MHz output clock of CKo2. FPo3: Programmable 8 kHz frame pulse corresponding to 4.096 MHz, 8.192 MHz, 16.384 MHz, or 32.768 MHz output clock of CKo3. Generated Offset Frame Pulse Outputs 0 to 2 (5 V-Tolerant Three-state Outputs) Individually programmable 8 kHz frame pulses, offset from the output frame boundary by a programmable number of channels. ST-BUS/GCI-Bus Clock Outputs 0 to 3 (5 V-Tolerant Three-state Outputs) CKo0: 4.096 MHz output clock. CKo1: 8.192 MHz output clock. CKo2: 16.384 MHz output clock. CKo3: 4.096 MHz, 8.192 MHz or 16.384 MHz programmable output clock. 32.768 MHz if in multiplied clock mode.
G15, G14, E15, F14
102, 106, 110, 112
FPo0 - 3
H14, D11, F15
100, 104, 108
FPo_OFF0 - 2
B7, C7, B5, J6
170, 172, 174, 227
CKo0 - 3
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Zarlink Semiconductor Inc.
ZL50020
PBGA Pin Number B10 LQFP Pin Number 155 Pin Name FPi Description
Data Sheet
ST-BUS/GCI-Bus Frame Pulse Input (5 V-Tolerant Schmitt-Triggered Input) This pin accepts the frame pulse which stays active for 61 ns, 122 ns or 244 ns at the frame boundary. The frame pulse frequency is 8 kHz. The frame pulse associated with the CKi must be applied to this pin. If the data rate is 16.384 Mbps, a 61 ns wide frame pulse must be used. By default, the device accepts a negative frame pulse in ST-BUS format, but it can accept a positive frame pulse instead if the FPINP bit is set high in the Control Register (CR). It can accept a GCI-formatted frame pulse by programming the FPINPOS bit in the Control Register (CR) to high. ST-BUS/GCI-Bus Clock Input (5 V-Tolerant Schmitt-Triggered Input) This pin accepts a 4.096 MHz, 8.192 MHz or 16.384 MHz clock. In divided clock mode the clock frequency applied to this pin must be twice the highest input or output data rate. In multiplied clock frequency applied to this pin must be twice the highest input data rate. The exception is, when data is running at 16.384 Mbps, a 16.384 MHz clock must be used. In multiplied clock mode the clock frequency applied to this pin must be twice the highest input data rate must be applied to STi/STio. When data is running at 16.384 Mbps, a 16.384 MHz clock must be used. By default, the clock falling edge defines the input frame boundary, but the device allows the clock rising edge to define the frame boundary by programming the CKINP bit in the Control Register (CR). Serial Input Streams 0 to 31 (5 V-Tolerant Inputs with Internal Pull-downs) The data rate of each input stream can be selected independently using the Stream Input Control Registers (SICR[n]). In the 2.048 Mbps mode, these pins accept serial TDM data streams at 2.048 Mbps with 32 channels per frame. In the 4.096 Mbps mode, these pins accept serial TDM data streams at 4.096 Mbps with 64 channels per frame. In the 8.192 Mbps mode, these pins accept serial TDM data streams at 8.192 Mbps with 128 channels per frame. In the 16.384 Mbps mode, these pins accept TDM data streams at 16.384 Mbps with 256 channels per frame.
B11
154
CKi
B6, C6, D5, D4, B4, B3, C5, C4, E3, C2, B2, D2, F3, F4, E2, F2, E1, D1, G1, F1, J1, H1, K1, L1, A7, A5, A6, A4, A3, A2, C1, B1
179, 180, 181, 182, 183, 184, 185, 187, 198, 200, 201, 202, 203, 204, 205, 206, 243, 244, 245, 246, 247, 248, 250, 252, 189, 190, 191, 192, 193, 194, 196, 197
STi0 - 31
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Zarlink Semiconductor Inc.
ZL50020
PBGA Pin Number N4, P4, R4, P5, N13, P11, R14, R15, M15, L15, L13, L14, E14, D13, D15, C15, D16, E16, C16, B16, A13, A12, A10, A11, N1, M1, P1, R1, T2, T3, T5, T4 R3, P6, R5, N5, P12, N15, P13, P15, N16, M16, L16, K16, H16, J16, G16, F16 B15 LQFP Pin Number 6, 7, 9, 10, 51, 52, 53, 54, 70, 72, 73, 74, 115, 116, 117, 118, 125, 126, 127, 128, 129, 130, 131, 132, 253, 254, 255, 256, 1, 2, 3, 4 11, 12, 13, 14, 55, 56, 58, 59, 75, 76, 77, 78, 119, 120, 122, 124 141 Pin Name STio0 - 31 Description
Data Sheet
Serial Output Streams 0 to 31 (5 V-Tolerant Slew-Rate-Limited Three-state I/Os with Enabled Internal Pull-downs) The data rate of each output stream can be selected independently using the Stream Output Control Registers (SOCR[n]). In the 2.048 Mbps mode, these pins output serial TDM data streams at 2.048 Mbps with 32 channels per frame. In the 4.096 Mbps mode, these pins output serial TDM data streams at 4.096 Mbps with 64 channels per frame. In the 8.192 Mbps mode, these pins output serial TDM data streams at 8.192 Mbps with 128 channels per frame. In the 16.384 Mbps mode, these pins output serial TDM data streams at 16.384 Mbps with 256 channels per frame.These output streams can be used as bi-directionals by programming BDH (bit 7) and BDL (bit 6) of Internal Mode Selection (IMS) register.
STOHZ0 - 15
Serial Output Streams High Impedance Control 0 to 15 (5 V-Tolerant Slew-Rate-Limited Three-state Outputs) These pins are used to enable (or disable) external three-state buffers. When an output channel is in the high impedance state, the STOHZ drives high for the duration of the corresponding output channel. When the STio channel is active, the STOHZ drives low for the duration of the corresponding output channel. STOHZ outputs are available for STio0 - 15 only. Output Drive Enable (5 V-Tolerant Input with Internal Pull-up) This is the output enable control for STio0 - 31 and the output-driven-high control for STOHZ0 - 15. When it is high, STio0 - 31 and STOHZ0 - 15 are enabled. When it is low, STio0 - 31 are tristated and STOHZ0 - 15 are driven high. Data Bus 0 to 15 (5 V-Tolerant Slew-Rate-Limited Three-state I/Os) These pins form the 16-bit data bus of the microprocessor port.
ODE
M4, N6, R6, P7, R7, N7, M8, N8, P8, R8, M9, N9, R9, N10, P9, R10
16, 18, 20, 22, 23, 24, 25, 26, 27, 28, 30, 32, 34, 36, 37, 38
D0 - 15
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Zarlink Semiconductor Inc.
ZL50020
PBGA Pin Number N12 LQFP Pin Number 44 Pin Name DTA_RDY Description
Data Sheet
Data Transfer Acknowledgment_Ready (5 V-Tolerant Three-state Output) This active low output indicates that a data bus transfer is complete for the Motorola interface. For the Intel interface, it indicates a transfer is completed when this pin goes from low to high. An external pull-up resistor MUST hold this pin at HIGH level for the Motorola mode. An external pull-down resistor MUST hold this pin at LOW level for the Intel mode. Chip Select (5 V-Tolerant Input) Active low input used by the Motorola or Intel microprocessor to enable the microprocessor port access. Read/Write_Write (5 V-Tolerant Input) This input controls the direction of the data bus lines (D0 - 15) during a microprocessor access. For the Motorola interface, this pin is set high and low for the read and write access respectively. For the Intel interface, a write access is indicated when this pin goes low. Data Strobe_Read (5 V-Tolerant Input) This active low input works in conjunction with CS to enable the microprocessor port read and write operations for the Motorola interface. A read access is indicated when it goes low for the Intel interface. Address 0 to 13 (5 V-Tolerant Inputs) These pins form the 14-bit address bus to the internal memories and registers.
R11
40
CS
N11
39
R/W_WR
R12
42
DS_RD
K13, K15, K14, J11, J12, J13, J15, H11, J14, H12, H13, H15, G12, G13 M13
82, 84, 86, 87, 88, 89, 90, 91, 92, 93, 94, 96, 98, 99 41
A0 - 13
MOT_INTEL
Motorola_Intel (5 V-Tolerant Input with Internal Pull-up) This pin selects the Motorola or Intel microprocessor interface to be connected to the device. When this pin is unconnected or connected to high, Motorola interface is assumed. When this pin is connected to ground, Intel interface should be used. Device Reset (5 V-Tolerant Input with Internal Pull-up) This input (active LOW) puts the device in its reset state that disables the STio0 - 31 drivers and drives the STOHZ0 - 15 outputs to high. It also preloads registers with default values and clears all internal counters. To ensure proper reset action, the reset pin must be low for longer than 1 s. Upon releasing the reset signal to the device, the first microprocessor access cannot take place for at least 600 s due to the time required to stabilize the device from the power-down state. Refer to Section Section 14.2 on page 32 for details.
G2
211
RESET
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Zarlink Semiconductor Inc.
ZL50020
4.0 Device Overview
Data Sheet
The device has thirty-two ST-BUS/GCI-Bus inputs (STi0 - 31) and thirty-two ST-BUS/GCI-Bus outputs (STio0 - 31). STio0 - 31 can also be configured as bi-directional pins, in which case STi0 - 31 will be ignored. It is a non-blocking digital switch with 2048 64 kbps channels and is capable of performing rate conversion between ST-BUS/GCI-Bus inputs and ST-BUS/GCI-Bus outputs. The ST-BUS/GCI-Bus inputs accept serial input data streams with data rates of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps on a per-stream basis. The ST-BUS/GCI-Bus outputs deliver serial data streams with data rates of 2.048 Mbps, 4.096 Mbps and, 8.192 Mbps and 16.384 Mbps on a per-stream basis. The device also provides sixteen high impedance control outputs (STOHZ0 - 15) to support the use of external ST-BUS/GCI-Bus tristate drivers for the first sixteen ST-BUS/GCI-Bus outputs (STio0 -15). By using Zarlink's message mode capability, microprocessor data stored in the connection memory can be broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and status information for external circuits or other ST-BUS/GCI-Bus devices. The device uses the ST-BUS/GCI-Bus input frame pulse (FPi) and the ST-BUS/GCI-Bus input clock (CKi) to define the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with various data rates. The output data streams will be driven by and have their timing defined by FPi and CKi in Divided Clock mode (CLKM bit 11 Table 14, Control Register (CR) Bits. In Multiplied Clock mode, the output data streams will be driven by an internally generated clock, which is multiplied from CKi internally. In Multiplied Clock mode, the output data streams will be driven by an internally generated clock, which is multiplied from CKi internally. Refer to Application Note ZLAN-120 (Mid Density Digital Switches Timing Modes) for further explanation of the different modes of operation. There are two clock modes for this device: The first is the Divided Clock mode. In this mode, output streams are clocked by input CKi. Therefore the output streams have exactly the same jitter as the input streams. The output data rate can be the same as or lower than the input data rate, but the output data rate cannot be higher than what CKi can drive. For example, if CKi is 4.096 MHz, the output data rate cannot be higher than 2.048 Mbps.The second clock mode is called Multiplied Clock mode. In this mode, CKi is used to generate a 16.384 MHz clock internally, and output streams are driven by this internal clock. In Multiplied Clock mode, the data rate of output streams can be any rate, but output jitter may not be exactly the same as input jitter. A Motorola or Intel compatible non-multiplexed microprocessor port allows users to program the device to operate in various modes under different switching configurations. Users can use the microprocessor port to perform internal register and memory read and write operations. The microprocessor port has a 16-bit data bus, a 14-bit address bus and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR and DTA_RDY). The device supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
5.0
Data Rates and Timing
The ZL50020 has 32 serial data inputs and 32 serial data outputs. Each stream can be individually programmed to operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Depending on the data rate there will be 32 channels, 64 channels, 128 channels or 256 channels, respectively, during a 125 s frame. The output streams can be programmed to operate as bi-directional streams. The output streams are divided into two groups to be programmed into bi-directional mode. By setting BDL (bit 6) in the Internal Mode Selection (IMS) register, input streams 0 - 15 (STi0 - 15) are internally tied low, and output streams 0 - 15 (STio0 - 15) are set to operate in a bi-directional mode. Similarly, when BDH (bit 7) in the Internal Mode Selection (IMS) register is set, input streams 16 - 31 (STi16 - 31) are internally tied low, and output streams 16 - 31 (STio16 - 31) are set to operate in bi-directional mode. The groups do not have to be set into the same mode. Therefore it is possible to have half of the streams operating in bi-directional mode while the other half is operating in normal input/output mode. The input data rate is set on a per-stream basis by programming STIN[n]DR3 - 0 (bits 3 - 0) in the Stream Input Control Register 0 - 31 (SICR0 - 31). The output data rate is set on a per-stream basis by programming STO[n]DR3 - 0 (bits 3 - 0) in the Stream Output Control Register 0 - 31 (SOCR0 - 31). The output data rates do not have to match or follow the input data rates. he maximum number of channels switched is limited to 2048 channels. If all 32
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
input streams were operating at 16.384 Mbps (256 channels per stream), this would result in 8192 channels. Memory limitations prevent the device from operating at this capacity. A maximum capacity of 2048 channels will occur if eight of the streams are operating at 16.384 Mbps, half of the streams are operating at 8.192 Mbps or all streams operating at 4.096 Mbps. With all streams operating at 2.048 Mbps, the capacity will be reduced to 1024 channels. However, as each stream can be programmed to a different data rate, any combination of data rates can be achieved, as long as the total channel count does not exceed 2048 channels. It should be noted that only full stream can be programmed for use. The device does not allow fractional streams. External High Impedance Control, STOHZ0 - 15. There are 16 external high impedance control signals, STOHZ0 - 15, that are used to control the external drivers for per-channel high impedance operations. Only the first sixteen ST-BUS/GCI-Bus (STio0 - 15) outputs are provided with corresponding STOHZ signals. The STOHZ outputs deliver the appropriate number of control timeslot channels based on the output stream data rate. Each control timeslot lasts for one channel time. When the ODE pin is high and the OSB (bit 2) of the Control Register (CR) is also high, STOHZ0 - 15 are enabled. When the ODE pin, OSB (bit 2) of the Control Register (CR) or the RESET pin is low, STOHZ0 - 15 are driven high, together with all the ST-BUS/GCI-Bus outputs being tristated. Under normal operation, the corresponding STOHZ outputs of any unused ST-BUS/GCI-Bus channel (high impedance) are driven high. Refer to Figure 16 on page 27 for a diagrammatical explanation.
5.1
Input Clock (CKi) and Input Frame Pulse (FPi) Timing
The frequency of the input clock (CKi) for the ZL50020 depends on the timing mode selected. In divided clock mode CKi, must be at least twice the highest input or output data rate. For example, if the highest input data rate is 4.096 Mbps and the highest output data rate is 8.192 Mbps, the input clock, CKi, must be 16.384 MHz, which is twice the highest overall data rate. The only exception to this is for 16.384 Mbps input or output data. In this case, the input clock, CKi, is equal to the data rate. The input frame pulse, FPi, must always follow CKi. In multiplied clock mode the frequency of CKi must be at least twice the highest input data rate regardless of the output data rate. An APLL is used to multiple CKi to generate an internal clock that is used to clock the output clocks and STio streams. Following the example above, if the highest input data rate is 4.096 Mbps, the input clock, CKi, must be 8.192 MHz, regardless of the output data rate. The only exception to this is for 16.384 Mbps input or output data. In this case, the input clock, CKi, is equal to the data rate. The input frame pulse, FPi, must always follow CKi. In either mode the user has to program the CKIN1 - 0 (bits 6 - 5) in the Control Register (CR) to indicate the width of the input frame pulse and the frequency of the input clock supplied to the device. Highest Input or Output Data Rate 16.384 Mbps or 8.192 Mbps 4.096 Mbps 2.048 Mbps
CKIN 1-0 Bits 00 01 10
Input Clock Rate (CKi) 16.384 MHz 8.192 MHz 4.096 MHz
Input Frame Pulse (FPi) 8 kHz (61 ns wide pulse) 8 kHz (122 ns wide pulse) 8 kHz (244 ns wide pulse)
Table 1 - CKi and FPi Configurations Highest Input or Output Data Rate 8.192 Mbps or 16.384 Mbps 4.096 Mbps 2.048 Mbps CKIN 1-0 Bits 00 01 10 Input Clock Rate (CKi) 16.384 MHz 8.192 MHz 4.096 MHz Input Frame Pulse (FPi) 8 kHz (61 ns wide pulse) 8 kHz (122 ns wide pulse) 8 kHz (244 ns wide pulse)
Table 2 - CKi and FPi Configurations for Divided Clock Modes
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Zarlink Semiconductor Inc.
ZL50020
Highest Input Data Rate 8.192 Mbps or 16.384 Mbps 4.096 Mbps 2.048 Mbps CKIN 1-0 Bits 00 01 10 Input Clock Rate (CKi) 16.384 MHz 8.192 MHz 4.096 MHz
Data Sheet
Input Frame Pulse (FPi) 8 kHz (61 ns wide pulse) 8 kHz (122 ns wide pulse) 8 kHz (244 ns wide pulse)
Table 3 - CKi and FPi Configurations for Multiplied Clock Mode The ZL50020 accepts positive and negative ST-BUS/GCI-Bus input clock and input frame pulse formats via the programming of CKINP (bit 8) and FPINP (bit 7) in the Control Register (CR). By default, the device accepts the negative input clock format and ST-BUS format frame pulses. However, the switch can also accept a positive-going clock format by programming CKINP (bit 8) in the Control Register (CR). A GCI-Bus format frame pulse can be used by programming FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR).
ST-BUS GCI-Bus
FPi (244 ns) FPINP = 0 FPINPOS = 0 FPi (244 ns) FPINP = 1 FPINPOS = 0 FPi (244 ns) FPINP = 0 FPINPOS = 1 FPi (244 ns) FPINP = 1 FPINPOS = 1 CKi (4.096 MHz) CKINP = 0 CKi (4.096 MHz) CKINP = 1 Channel 0 STi (2.048 Mbps) Channel 31
0
7
6
1
0
7
Figure 4 - Input Timing when CKIN1 - 0 bits = "10" in the CR
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Zarlink Semiconductor Inc.
ZL50020
FPi (122 ns) FPINP = 0 FPINPOS = 0 FPi (122 ns) FPINP = 1 FPINPOS = 0 FPi (122 ns) FPINP = 0 FPINPOS = 1 GCI-Bus FPi (122 ns) FPINP = 1 FPINPOS = 1 CKi (8.192 MHz) CKINP = 0 CKi (8.192 MHz) CKINP = 1 Channel 0 STi (4.096 Mbps) Channel 63
Data Sheet
ST-BUS
1
0
7
6
5
4
2
1
0
7
6
Figure 5 - Input Timing when CKIN1 - 0 bits = "01" in the CR
ST-BUS GCI-Bus
FPi (61 ns) FPINP = 0 FPINPOS = 0 FPi (61 ns) FPINP = 1 FPINPOS = 0 FPi (61 ns) FPINP = 0 FPINPOS = 1 FPi (61 ns) FPINP = 1 FPINPOS = 1 CKi (16.384 MHz) CKINP = 0 CKi (16.384 MHz) CKINP = 1 Channel 0 STi (8.192 Mbps) STi (16.384 Mbps) Channel N = 127
107654 321
Channel 0
54 3 2 1 0 7 65
Channel N = 255
321076543210765432
321076543210765432
Figure 6 - Input Timing when CKIN1 - 0 = "00" in the CR
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Zarlink Semiconductor Inc.
ZL50020
6.0 ST-BUS and GCI-Bus Timing
Data Sheet
The ZL50020 is capable of operating using either the ST-BUS or GCI-Bus standards. The output timing that the device generates is defined by the bus standard. In the ST-BUS standard, the output frame boundary is defined by the falling edge of CKo while FPo is low. In the GCI-Bus standard, the frame boundary is defined by the rising edge of CKo while FPo goes high. The data rates define the number of channels that are available in a 125 s frame pulse period. By default, the ZL50020 is configured for ST-BUS input and output timing. To set the input timing to conform to the GCI-Bus standard, FPINPOS (bit 9) and FPINP (bit 7) in the Control Register (CR) must be set. To set output timing to conform to the GCI-Bus standard, FPO[n]P and FPO[n]POS must be set in the Output Clock and Frame Pulse Selection Register (OCFSR). The CKO[n]P bits in the Output Clock and Frame Pulse Selection Register control the polarity (positive-going or negative-going) of the output clocks.
7.0
Output Timing Generation
The ZL50020 generates frame pulse and clock timing. There are four output frame pulse pins (FPo0 - 3) and four output clock pins (CKo0 - 3). All output frame pulses are 8 kHz output signals. By default, the output frame boundary is defined by the falling edge of the CKo0, while FPo0 is low. At the output frame boundary, the CKo1, CKo2 and CKo3 output clocks will by default have a falling edge, while FPo1, FPo2 and FPo3 will be low. The duration of the frame pulse low cycle and the frequency of the corresponding output clock are shown in Table 4 on page 19. Every frame pulse and clock output can be tristated by programming the enable bits in the Internal Mode Selection (IMS) register. Pin Name FPo0 pulse width CKo0 FPo1 pulse width CKo1 FPo2 pulse width CKo2 FPo3 pulse width CKo3 Output Timing Rate 244 4.096 122 8.192 61 16.384 244, 122, 61 or 30 4.096, 8.192, 16.384 or 32.768 Table 4 - Output Timing Generation The output timing is dependent on the timing mode that is selected. When the device is in Divided Clock mode, the frequencies on CKo0 - 3 cannot be greater than the input clock, CKi. For example, if the input clock is 8.192 MHz, the CKo2 pin will not produce a valid output clock and the CKo3 pin can only be programmed to output a 4.096 MHz or 8.192 MHz clock signal. The device also delivers positive or negative output frame pulse and ST-BUS/GCI-Bus output clock formats via the programming of various bits in the Output Clock and Frame Pulse Selection Register (OCFSR). By default, the device delivers the negative output clock format. The ZL50020 can also deliver GCI-Bus format output frame pulses by programming bits of the Output Clock and Frame Pulse Selection Register (OCFSR). As there is a separate bit setting for each frame pulse output, some of the outputs can be set to operate in ST-BUS mode and others in GCI-Bus mode. The following figures describe the usage of the FPO0P, FPO1P, FPO2P, FPO3P, CKO0P, CKO1P, CKO2P and CKO3P bits to generate the FPo0 - 3 and CKo0 - 3 timing. Output Timing Unit ns MHz ns MHz ns MHz ns MHz
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Zarlink Semiconductor Inc.
ZL50020
ST-BUS CKOFPO0EN = 1 FPO0P = 0 FPO0POS = 0 CKOFPO0EN = 1 FPO0P = 1 FPO0POS = 0 CKOFPO0EN = 1 FPO0P = 0 FPO0POS = 1 GCI-Bus CKOFPO0EN = 1 FPO0P = 1 FPO0POS = 1 CKOFPO0EN = 1 CKO0P = 0 CKo0 = 4.096 MHz CKOFPO0EN = 1 CKO0P = 1 CKo0 = 4.096 MHz
Data Sheet
Figure 7 - Output Timing for CKo0 and FPo0
ST-BUS GCI-Bus
CKOFPO1EN = 1 FPO1P = 0 FPO1POS = 0 CKOFPO1EN = 1 FPO1P = 1 FPO1POS = 0 CKOFPO1EN = 1 FPO1P = 0 FPO1POS = 1 CKOFPO1EN = 1 FPO1P = 1 FPO1POS = 1 CKOFPO1EN = 1 CKO1P = 0 CKo1 = 8.192 MHz CKOFPO1EN = 1 CKO1P = 1 CKo1 = 8.192 MHz
Figure 8 - Output Timing for CKo1 and FPo1
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Zarlink Semiconductor Inc.
ZL50020
ST-BUS CKOFPO2EN = 1 FPO2P = 0 FPO2POS = 0 CKOFPO2EN = 1 FPO2P = 1 FPO2POS = 0 CKOFPO2EN = 1 FPO2P = 0 FPO2POS = 1 GCI-Bus CKOFPO2EN = 1 FPO2P = 1 FPO2POS = 1
Data Sheet
CKOFPO2EN = 1 CKO2P = 0 CKo2 = 16.384 MHz CKOFPO2EN = 1 CKO2P = 1 CKo2 = 16.384 MHz
Figure 9 - Output Timing for CKo2 and FPo2
CKOFPO3EN = 1 CKOFPO3SEL1-0 = 11 FPO3P = 0 FPO3POS = 0 CKOFPO3EN = 1 CKOFPO3SEL1-0 = 11 FPO3P = 1 FPO3POS = 0 CKOFPO3EN = 1 CKOFPO3SEL1-0 = 11 FPO3P = 0 FPO3POS = 1 CKOFPO3EN = 1 CKOFPO3SEL1-0 = 11 FPO3P = 1 FPO3POS = 1 CKOFPO3EN = 1 CKOFPO3SEL1-0 = 11 CKO3P = 0 CKo3 = 32.768 MHz CKOFPO3EN = 1 CKOFPO3SEL1-0 = 11 CKO3P = 1 CKo3 = 32.768 MHz
GCI-Bus
ST-BUS
NOTE: When CKOFPO3SEL1-0 = "00," the output for FPo3 and CKo3 follow the same as Figure 7: Output Timing for CKo0 and FPo0 When CKOFPO3SEL1-0 = "01," the output for FPo3 and CKo3 follow the same as Figure 8: Output Timing for CKo1 and FPo1 When CKOFPO3SEL1-0 = "10," the output for FPo3 and CKo3 follow the same as Figure 9: Output Timing for CKo2 and FPo2
Figure 10 - Output Timing for CKo3 and FPo3 with CK0FPo3SEL1-0="11"
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Zarlink Semiconductor Inc.
ZL50020
8.0 Data Input Delay and Data Output Advancement
Data Sheet
Various registers are provided to adjust the input delay and output advancement for each input and output data stream. The input bit delay and output bit advancement can vary from 0 to 7 bits for each individual stream. If input delay of less than a bit is desired, different sampling points can be used to handle the adjustments. The sampling point can vary from 1/4 to 4/4 with a 1/4-bit increment for all input streams, unless the stream is operating at 16.384 Mbps, in which case the fractional bit delay has a 1/2-bit increment. By default, the sampling point is set to the 3/4-bit location for non-16.384 Mbps data rates and the 1/2-bit location for the 16.384 Mbps data rate. The fractional output bit advancement can vary from 0 to 3/4 bits, again with a 1/4-bit increment unless the output stream is operating at 16.384 Mbps, in which case the output bit advancement has a 1/2-bit increment from 0 to 1/2 bit. By default, there is 0 output bit advancement. Although input delay or output advancement features are available on streams which are operating in bi-directional mode it is not recommended, as it can easily cause bus contention. If users require this function, special attention must be given to the timing to ensure contention is minimized.
8.1
Input Bit Delay Programming
The input bit delay programming feature provides users with the flexibility of handling different wire delays when designing with source streams for different devices. By default, all input streams have zero bit delay, such that bit 7 is the first bit that appears after the input frame boundary (assuming ST-BUS formatting). The input delay is enabled by STIN[n]BD2-0 (bits 8 - 6) in the Stream Input Control Register 0 - 31 (SICR0 - 31) as described in Table 25 on page 49. The input bit delay can range from 0 to 7 bits.
FPi Last Channel STi[n] Bit Delay = 0 (Default) Channel 0 Channel 1 Channel 2
432107654321076543210765432
Bit Delay = 1 Last Channel Channel 2
STi[n] Bit Delay = 1
Channel 0
Channel 1
543210765432107654321076543
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, and 8.192 and 16.384 Mbps modes respectively.
Figure 11 - Input Bit Delay Timing Diagram (ST-BUS)
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Zarlink Semiconductor Inc.
ZL50020
8.2 Input Bit Sampling Point Programming
Data Sheet
In addition to the input bit delay feature, theZL50020 allows users to change the sampling point of the input bit by programming STIN[n]SMP 1-0 (bits 5 - 4) in the Stream Input Control Register 0 - 31 (SICR0 - 31). For input streams operating at any rate except 16.384 Mbps, the default sampling point is at 3/4 bit and users can change the sampling point to 1/4, 1/2, 3/4 or 4/4 bit position. When the stream is operating at 16.384 Mbps, the default sampling point is 1/2 bit and can be adjusted to a 4/4 bit position.
FPi Sampling Point = 3/4 Bit Channel 0
STi[n] STIN[n]SMP1-0 = 00 (2, 4 or 8 Mbps Default) STi[n] STIN[n]SMP1-0 = 01 (2, 4 or 8 Mbps) STi[n] STIN[n]SMP1-0 = 10 (2, 4 or 8 Mbps) STIN[n]SMP1-0 = 00 (16 Mbps - Default) STi[n] STIN[n]SMP1-0 = 11 (2, 4 or 8 Mbps) STIN[n]SMP1-0 = 10 (16 Mbps)
Last Channel
2
1
0
7
6
Sampling Point = 1/4 Bit Channel 0
5
Last Channel
1
0
Last Channel
7
6
5
Sampling Point = 1/2 Bit Channel 0
1
Last Channel
0
7
6
5
Sampling Point = 4/4 Bit Channel 0
2
1
0
7
6
5
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps mode respectively
Figure 12 - Input Bit Sampling Point Programming
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
The input delay is controlled by STIN[n]BD2-0 (bits 8 - 6) to control the bit shift and STIN[n]SMP1 - 0 (bits 5 - 4) to control the sampling point in the Stream Input Control Register 0 - 31 (SICR0 - 31).
Nominal Channel n Boundary Nominal Channel n+1 Boundary
STi[n]
0
7
6
5
4
3
2
1
0
7 111 11 111 00 111 10 111 01 110 11 110 00 110 10 110 01 101 11 101 00 101 10 101 01 100 11 100 00 100 10 100 01
000 01 000 10 000 00 (Default) 000 11 001 01 001 10 001 00 001 11 010 01 010 10 010 00 010 11 011 01 011 10 011 00 011 11
The first 3 bits represent STIN[n]BD2 - 0 for setting the bit delay The second set of 2 bits represent STIN[n]SMP1 - 0 for setting the sampling point offset Example: With a setting of 011 10 the offset will be 3 bits at a 1/2 sampling point Note: Italic settings can be used in 16 Mbps mode (1/2 and 4/4 sampling point)
Figure 13 - Input Bit Delay and Factional Sampling Point
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Zarlink Semiconductor Inc.
ZL50020
8.3 Output Advancement Programming
Data Sheet
This feature is used to advance the output data of individual output streams with respect to the output frame boundary. Each output stream has its own bit advancement value which can be programmed in the Stream Output Control Register 0 - 31 (SOCR0 - 31). By default, all output streams have zero bit advancement such that bit 7 is the first bit that appears after the output frame boundary (assuming ST-BUS formatting). The output advancement is enabled by STO[n]AD 2 - 0 (bits 6 - 4) of the Stream Output Control Register 0 - 31 (SOCR0 - 31) as described in Table 27 on page 53. The output bit advancement can vary from 0 to 7 bits.
FPi Channel 2
Last Channel STio[n] Bit Adv = 0 (Default)
Channel 0
Channel 1
432107654321076543210765432
Bit Advancement = 1 Last Channel Channel 0 Channel 1 Channel 2
STio[n] Bit Adv = 1
321076543210765432107654321
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
Figure 14 - Output Bit Advancement Timing Diagram (ST-BUS)
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Zarlink Semiconductor Inc.
ZL50020
8.4 Fractional Output Bit Advancement Programming
Data Sheet
In addition to the output bit advancement, the device has a fractional output bit advancement feature that offers better resolution. The fractional output bit advancement is useful in compensating for varying parasitic load on the serial data output pins. By default all of the streams have zero fractional bit advancement such that bit 7 is the first bit that appears after the output frame boundary. The fractional output bit advancement is enabled by STO[n]FA 1 - 0 (bits 8 - 7) in the Stream Output Control Register 0 - 31 (SOCR0 - 31). For all streams running at any data rate except 16.384 Mbps the fractional bit advancement can vary from 0, 1/4, 1/2 to 3/4 bits. For streams operating at 16.384 Mbps, the fractional bit advancement can be set to either 0 or 1/2 bit.
FPi
Last Channel STio[n] STo[n]FA1-0 = 00 (Default 2, 4, 8 or 16Mb/s) STio[n] STo[n]FA1-0 = 01 (2, 4 or 8 Mbps) STio[n] STo[n]FA1-0 = 10 (2, 4 or 8 Mbps) STo[n]FA1-0 = 01 (16 Mbps)
Channel 0
2
1
Last Channel
0
7
6
Channel 0
5
Fractional Bit Advancement = 1/4 Bit
1
0
7
6
5
4
Fractional Bit Advancement = 1/2 Bit Last Channel Channel 0
1
0
7
6
5
4
Fractional Bit Advancement = 3/4 Bit STio[n] STo[n]FA1-0 = 11 (2, 4 or 8 Mbps) Last Channel Channel 0
1
0
7
6
5
4
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
Figure 15 - Output Fractional Bit Advancement Timing Diagram (ST-BUS)
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Zarlink Semiconductor Inc.
ZL50020
8.5 External High Impedance Control Advancement
Data Sheet
The external high impedance signals can be programmed to better match the timing required by the external buffers. By default, the output timing of the STOHZ signals follows the programmed channel delay and bit offset of their corresponding ST-BUS/GCI-Bus output streams. In addition, for all high impedance streams operating at any data rate except 16.384 Mbps, the user can advance the STOHZ signals a further 0, 1/4, 1/2, 3/4 or 4/4 bits by programming STOHZ[n]A 2 - 0 (bit 11 - 9) in the Stream Output Control Register. When the stream is operating at 16.384 Mbps, the additional STOHZ advancement can be set to 0, 1/2 or 4/4 bits by programming the same register.
FPi HiZ STio[n] Last CH0 CH1 CH2 CH3 Last-2 Last-1 Last CH0
STOHZ Advancement (Programmable in 4 steps of 1/4 bit for 2.048 Mbps, 4.096 Mbps and 8.192 Mbps Programmable in 2 steps of 1/2 bit for 16.384 Mbps) STOHZ[n] (Default = No Advancement) STOHZ[n] (with Advancement) Output Frame Boundary Note: n = 0 to 15 Note: Last = Last Channel of 31, 63, 127 and 255 for 2.048 Mbps, 4.096 Mbps. 8.192 Mbps and 16.384 Mbps modes respectively.
Figure 16 - Channel Switching External High Impedance Control Timing
9.0
Data Delay Through the Switching Paths
The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform timeslot interchange functions with different throughput delay capabilities on a per-channel basis. For voice applications, select variable throughput delay to ensure minimum delay between input and output data. In wideband data applications, select constant delay to maintain the frame integrity of the information through the switch. The delay through the device varies according to the type of throughput delay selected by the V/C (bit 14) in the Connection Memory Low when CMM = 0.
9.1
Variable Delay Mode
Variable delay mode causes the output channel to be transmitted as soon as possible. This is a useful mode for voice applications where the minimum throughput delay is more important than frame integrity. The delay through the switch can vary from 7 channels to 1 frame + 7 channels. To set the device into variable delay mode, VAREN (bit 4) in the Control Register (CR) must be set before V/C (bit 14) in the Connection Memory Low when CMM = 0. If the VAREN bit is not set and the device is programmed for variable delay mode, the information read on the output stream will not be valid.
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Zarlink Semiconductor Inc.
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Data Sheet
In variable delay mode, the delay depends on the combination of the source and destination channels of the input and output streams. m = input channel number n = output channel number T = Delay between input and output n-m <= 0 1 frame - (m-n) 0 < n-m < 7 STio < STi 1 frame + (n-m) Table 5 - Delay for Variable Delay Mode For example, if Stream 4 Channel 2 is switched to Stream 5 Channel 9 with variable delay, the data will be output in the same 125 s frame. Contrarily, if Stream 6 Channel 1 is switched to Stream 9 Channel 3, the information will appear in the following frame.
Frame N Frame N + 1
n-m = 7 STio >= STi n-m
n-m > 7
STi4 CH2
L-2
L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2
L-1 CH0 CH1 CH2 CH3
STio5 CH9
L-2
L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2
L-1 CH0 CH1 CH2 CH3
STi6 CH1
L-2
L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2
L-1 CH0 CH1 CH2 CH3
STio9 CH3
L-2
L-1 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9
L-2
L-1 CH0 CH1 CH2 CH3
L = last channel = 31, 63, 127, or 255 for 2.048 Mbps, 4.096 Mbps 8.192 Mbps, or 16.384 Mbps respectively
Figure 17 - Data Throughput Delay for Variable Delay
9.2
Constant Delay Mode
In this mode, frame integrity is maintained in all switching configurations. The delay though the switch is 2 frames Input Channel + Output Channel. This can result in a minimum of 1 frame + 1 channel delay if the last channel on a stream is switched to the first channel of a stream. The maximum delay is 3 frames - 1 channel. This occurs when the first channel of a stream is switched to the last channel of a stream. The constant delay mode is available for all output channels. The data throughput delay is expressed as a function of ST-BUS/GCI-Bus frames, input channel number (m) and output channel number (n). The data throughput delay (T) is: T = 2 frames + (n - m) The constant delay mode is controlled by V/C (bit 14) in the Connection Memory Low when CMM = 0. When this bit is set low, the channel is in constant delay mode. If VAREN (bit 4) in the Control Register (CR) is set (to enable variable throughput delay on a chip-wide basis), the device can still be programmed to operate in constant delay mode.
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Zarlink Semiconductor Inc.
ZL50020
Frame N Frame N + 1
Data Sheet
Frame N + 2
STi
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
STio
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
STi
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
STio
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L-2
L-1 CH0 CH1 CH2 CH3
L = last channel = 31, 63, 127, or 255 for 2.048 Mbps, 4.096 Mbps 8.192 Mbps, or 16.384 Mbps respectively
Figure 18 - Data Throughput Delay for Constant Delay
10.0
Connection Memory Description
The connection memory consists of two blocks, Connection Memory Low (CM_L) and Connection Memory High (CM_H). The CM_L is 16 bits wide and is used for channel switching and other special modes. The CM_H is 5 bits wide and is used for the voice coding function. When UAEN (bit 15) of the Connection Memory Low (CM_L) is low, -law/A-law conversion will be turned off and the contents of CM_H will be ignored. Each connection memory location of the CM_L or CM_H can be read or written via the 16 bit microprocessor port within one microprocessor access cycle. See Table 32 on page 56 for the address mapping of the connection memory. Any unused bits will be reset to zero on the 16-bit data bus. For the normal channel switching operation, CMM (bit 0) of the Connection Memory Low (CM_L) is programmed low. SCA7 - 0 (bits 8 - 1) indicate the source (input) channel address and SSA4 - 0 (bits 13 - 9) indicate the source (input) stream address. The 5-bit contents of the CM_H will be ignored during the normal channel switching mode without the -law/A-law conversion when UAEN (bit 15) of the Connection Memory Low (CM_L) is set to zero. If -law/A-law conversion is required, the CM_H bits must be programmed first to provide the voice/data information, the input coding law and the output coding law before the assertion of UAEN (bit 15) in the Connection Memory Low. When CMM (bit 0) of the Connection Memory Low (CM_L) is programmed high, the ZL50020 will operate in one of the special modes described in Table 34 on page 57. When the per-channel message mode is enabled, MSG7 - 0 (bit 10 - 3) in the Connection Memory Low (CM_L) will be output via the serial data stream as message output data. When the per-channel message mode is enabled, the -law/A-law conversion can also be enabled as required.
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Zarlink Semiconductor Inc.
ZL50020
11.0 Connection Memory Block Programming
Data Sheet
This feature allows for fast initialization of the connection memory after power up.
11.1
Memory Block Programming Procedure
1. Set MBPE (bit 3) in the Control Register (CR) from low to high. 2. Configure BPD2 - 0 (bits 3 - 1) in the Internal Mode Selection (IMS) register to the desired values to be loaded into CM_L. 3. Start the block programming by setting MBPS (bit 0) in the Internal Mode Selection Register (IMS) high. The values stored in BPD2 - 0 will be loaded into bits 2 - 0 of all CM_L positions. The remaining CM_L locations (bits 15 - 3) and the programmable values in the CM_H (bits 4 - 0) will be loaded with zero values. The following tables show the resulting values that are in the CM_L and CM_H connection memory locations. Bit Value 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 BPD2 1 BPD1 0 BPD0
Table 6 - Connection Memory Low After Block Programming
Bit Value
15 0
14 0
13 0
12 0
11 0
10 0
9 0
8 0
7 0
6 0
5 0
4 0
3 0
2 0
1 0
0 0
Table 7 - Connection Memory High After Block Programming Note: Bits 15 to 5 are reserved in Connection Memory High and should always be 0. It takes at least two frame periods (250 s) to complete a block program cycle. MBPS (bit 0) in the Control Register (CR) will automatically reset to a low position after the block programming process has completed. MBPE (bit 3) in the Internal Mode Selection (IMS) register must be cleared from high to low to terminate the block programming process. This is not an automatic action taken by the device and must be performed manually. Note: Once the block program has been initiated, it can be terminated at any time prior to completion by setting MBPS (bit 0) in the Control Register (CR) or MBPE (bit 3) in the Internal Mode Selection (IMS) register to low. If the MBPE bit was used to terminate the block programming, the MBPS bit will have to be set low before enabling other device operations.
12.0
Device Performance Divided Clock and Multiplied Clock Modes
This device has two main operating modes - Divided Clock mode and Multiplied Clock mode. In Multiplied Clock mode, output clocks and frame pulses are generated based on CKi and FPi. In Divided Clock mode, output clocks and frame pulses are directly divided from CKi/FPi; therefore, the output clock rate cannot exceed the CKi rate. In Multiplied Clock mode, the output clocks and frame pulses are generated from a clock internal to the device and are synchronized to CKi and FPi. All specified frequencies are available on CKo[0:3] in Multiplied Clock mode.
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
Table 8, "ZL50020 Operating Modes" on page 31 summarizes the different modes of operation available within the ZL50020. Each Major mode (explained below) has an associated Minor mode that is determined by setting the MODE_4M Input Control pins and the OPM bit in the Control Register (Table 14, "Control Register (CR) Bits" on page 38) indicated in the table.
Device Operating Mode Major Divided Clock Multiplied Clock Legend: X Don't care or not applicable. Minor 4M 8/16 M 4M 8/16 M Input Pins Control MODE_4M [1:0] 11 00 11 00 Signal CKi 4M 8/16 M 4M 8/16 M 1 CKi MULT CR Register Bit OPM 0 Output Clock Pins Reference Lock CKo0-3 CKi Enabled CKo0-3 Yes STi CKi Data Pins Clock Source STo CKo0-3 (CKi) CKo0-3 (CKi MULT)
Reference Lock Refers to what signal the output pins are locked to: Cki = Bypass. Cki is passed directly through to CKo0-3. Cki MULT = Cki is passed through clock multiplier to CKo0-3. Clock Source Refers to which clock samples STi and which clock outputs STo; STi applies when STio is input; STo applies when STio is output.
Table 8 - ZL50020 Operating Modes
12.1
Divided Clock Mode Performance
When the device is in Divided Clock mode, STio0 - 31 are driven by CKi. In this mode, the output streams and clocks have the same amount of jitter as the input clock (CKi), but the output data rate cannot exceed the input data rate defined by CKi. For example, if CKi is 4.096 MHz, the output data rate cannot be higher than 2.048 Mbps, and the generated output clock rates cannot exceed 4.096 MHz.
12.2
Multiplied Clock Mode Performance
When the device is in Multiplied Clock mode, device hardware is used to multiply CKi internally. STio0 - are driven by this internally generated clock. In this mode, the output data rate can be any specified data rate, but the output streams and clocks may have different jitter characteristics from the input clock (CKi). CKo0 CKo1 CKo2 CKo3 FPo0 FPo1 FPo2 FPo3 4.096 MHz 8.192 MHz 16.384 MHz 4.096 MHz, 8.192 MHz, 16.384 MHz or 32.768 MHz 8 kHz (244 ns wide pulse) 8 kHz (122 ns wide pulse) 8 kHz (61 ns wide pulse) 8 kHz (244 ns, 122 ns, 61 ns or 30 ns wide pulse) Table 9 - Generated Output Frequencies
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Zarlink Semiconductor Inc.
ZL50020
13.0 Microprocessor Port
Data Sheet
The device provides access to the internal registers, connection memories and data memories via the microprocessor port. The microprocessor port is capable of supporting both Motorola and Intel non-multiplexed microprocessors. The microprocessor port consists of a 16-bit parallel data bus (D15 - 0), 14 bit address bus (A13 0) and six control signals (MOT_INTEL, CS, DS_RD, R/W_WR and DTA_RDY). The data memory can only be read from the microprocessor port. For a data memory read operation, D7 - 0 will be used and D15 - 8 will output zeros. For a CM_L read or write operation, all bits (D15 - 0) of the data bus will be used. For a CM_H write operation, D4 0 of the data bus must be configured and D15 - 5 are ignored. D15 - 5 must be driven either high or low. For a CM_H read operation, D4 - 0 will be used and D15 - 5 will output zeros. Refer to Figure 20 on page 62, Figure 21 on page 63, Figure 22 on page 64 and Figure 23 on page 65 for the microprocessor timing.
14.0
* * * * *
Device Reset and Initialization
The RESET pin is used to reset the ZL50020. When this pin is low, the following functions are performed: synchronously puts the microprocessor port in a reset state tristates the STio0 - 31 outputs drives the STOHZ0 - 15 outputs to high preloads all internal registers with their default values (refer to the individual registers for default values) clears all internal counters
14.1
Power-up Sequence
The recommended power-up sequence is for the VDD_IO supply (normally +3.3 V) to be established before the power-up of the VDD_CORE supply (normally +1.8 V). The VDD_CORE supply may be powered up at the same time as VDD_IO, but should not "lead" the VDD_IO supply by more than 0.3 V.
14.2
Device Initialization on Reset
Upon power up, the ZL50020 should be initialized as follows: * * * * * * * * Set the ODE pin to low to disable the STio0 - 31 outputs and to drive STOHZ0 - 15 to high Set the TRST pin to low to disable the JTAG TAP controller Reset the device by pulsing the RESET pin to zero for longer than 1 s After releasing the RESET pin from low to high, wait for a certain period of time (see Note below) for the device to stabilize from the power down state before the first microprocessor port access can occur Program CKIN1 - 0 (bit 6 -5) in the Control Register (CR) to define the frequency of the CKi and FPi inputs Wait at least 500 s prior to the next microport access (see Note below) Use the block programming mode to initialize the connection memory Release the ODE pin from low to high after the connection memory is programmed
Note: If CKi is 16.384 MHz, the waiting time is 500 s; if CKi is 8.192 MHz, the waiting time is 1 ms; if CKi is 4.096 MHz, the waiting time is 2 ms.
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Zarlink Semiconductor Inc.
ZL50020
14.3 Software Reset
Data Sheet
In addition to the hardware reset from the RESET pin, the device can also be reset by using software reset SRSTSW (bit 1) in the Software Reset Register (SRR).
15.0
Pseudo Random Bit Generation and Error Detection
The ZL50020 has one Bit Error Rate (BER) transmitter and one BER receiver for each pair of input and output streams, resulting in 32 transmitters connected to the output streams and 32 receivers associated with the input streams. Each transmitter can generate a BER sequence with a pattern of 215-1 pseudorandom code (ITU O.151). Each transmitter can start at any location on the stream and will last for a minimum of 1 channel to a maximum of 1 frame time (125 s). The BER receivers and transmitters are enabled by programming the RBEREN (bit 5) and TBEREN (bit 4) in the IMS register. In order to save power, the 32 transmitters and/or receivers can be disabled. (This is the default state.) Multiple connection memory locations can be programmed for BER tests such that the BER patterns can be transmitted for multiple consecutive output channels. If consecutive input channels are not selected, the BER receiver will not compare the bit patterns correctly. The number of output channels which the BER pattern occupies has to be the same as the number of channels defined in the BER Length Register (BRLR) which defines how many BER channels are to be monitored by the BER receiver. For each input stream, there is a set of registers for the BER test. The registers are as follows: * * * BER Receiver Control Register (BRCR) - ST[n]CBER (bit 1) is used to clear the Bit Receiver Error Register (BRER). ST[n]SBER (bit 0) is used to enable the per-stream BER receiver. BER Receiver Start Register (BRSR) - ST[n]BRS7 - 0 (bit 7 - 0) defines the input channel from which the BER sequence will start to be compared. BER Receiver Length Register (BRLR) - ST[n]BL8 - 0 (bit 8 - 0) define how many channels the sequence will last. Depending on the data rate being used, the BER test can last for a maximum of 32, 64, 128 or 256channels at the data rates of 2.048, 4.096, 8.192or 16.384Mbps, respectively. The minimum length of the BER test is a single channel. The user must take care to program the correct channel length for the BER test so that the channel length does not exceed the total number of channels available in the stream. BER Receiver Error Register (BRER) - This read-only register contains the number of counted errors. When the error count reaches 0xFFFF, the BER counter will stop updating so that it will not overflow. ST[n]CBER (bit 1) in the BER Receiver Control Register is used to reset the BRER register.
*
For normal BER operation, CMM (bit 0) must be 1 in the Connection Memory Low (CM_L). PCC1 - 0 (bits 2 - 1) in the Connection Memory Low must be programmed to "10" to enable the per-stream based BER transmitters. For each stream, the length (or total number of channels) of BER testing can be as long as one whole frame, but the channels MUST be consecutive. Upon completion of programming the connection memory, the corresponding BER receiver can be started by setting ST[n]SBER (bit 0) in the BRCR to high. There must be at least 2 frames (250 s) between completion of connection memory programming and starting the BER receiver before the BER receiver can correctly identify BER errors. A 16 bit BER counter is used to count the number of bit errors.
16.0
PCM A-law/-law Translation
The ZL50020 provides per-channel code translation to be used to adapt pulse code modulation (PCM) voice or data traffic between networks which use different encoding laws. Code translation is valid in both Connection Mode and Message Mode. In order to use this feature, the Connection Memory High (CM_H) entry for the output channel must be programmed. V/D (bit 4) defines if the traffic in the channel is voice or data. Setting ICL1 - 0 (bits 3 - 2) programs the input coding law and OCL1 - 0 (bits 1- 0) programs the output coding law as shown in Table 10.
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Zarlink Semiconductor Inc.
ZL50020
The different code options are: Input Coding (ICL1- 0) 00 01 10 11 Output Coding (OCL1 - 0) 00 01 10 11 Voice Coding (V/D bit = 0) ITU-T G.711 A-law ITU-T G.711 -law A-law without Alternate Bit Inversion (ABI) -law without Magnitude Inversion (MI)
Data Sheet
Data Coding (V/D bit = 1) No code Alternate Bit Inversion (ABI) Inverted Alternate Bit Inversion (ABI) All bits inverted
Table 10 - Input and Output Voice and Data Coding For voice coding options, the ITU-T G.711 A-law and ITU-T G.711 -law are the standard rules for encoding. A-law without Alternate Bit Inversion (ABI) is an alternative code that does not invert the even bits (6, 4, 2, 0). -law without Magnitude Inversion (MI) is an alternative code that does not perform inversion of magnitude bits (6, 5, 4, 3, 2, 1, 0). When transferring data code, the option "no code" does not invert the bits. The Alternate Bit Inversion (ABI) option inverts the even bits (6, 4, 2, 0) while the Inverted Alternate Bit Inversion (ABI) inverts the odd bits (7, 5, 3, 1). When the "All bits inverted" option is selected, all of the bits (7, 6, 5, 4, 3, 2, 1, 0) are inverted. The input channel and output channel encoding law are configured independently. If the output channel coding is set to be different from the input channel, the ZL50020 performs translation between the two standards. If the input and output encoding laws are set to the same standard, no translation occurs. As the V/D (bit 4) of the Connection Memory High (CM_H) must be set on a per-channel basis, it is not possible to translate between voice and data encoding laws.
17.0
Quadrant Frame Programming
By programming the Stream Input Quadrant Frame Registers (SIQFR0 - 31), users can divide one frame of input data into four quadrant frames and can force the LSB or MSB of every input channel in these quadrants to one or zero for robbed-bit signaling. The four quadrant frames are defined as follows: Data Rate 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps Quadrant 0 Channel 0 - 7 Channel 0 - 15 Channel 0 - 31 Channel 0 - 63 Quadrant 1 Channel 8 - 15 Channel 16 - 31 Channel 32 - 63 Channel 64 - 127 Quadrant 2 Channel 16 - 23 Channel 32 - 47 Channel 64 - 95 Channel 128 - 191 Quadrant 3 Channel 24 - 31 Channel 48 - 63 Channel 96 - 127 Channel 192 - 255
Table 11 - Definition of the Four Quadrant Frames
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
When the quadrant frame control bits, STIN[n]Q3C2 - 0 (bit 11 - 9), STIN[n]Q2C2 - 0 (bit 8 - 6), STIN[n]Q1C2 - 0 (bit 5 - 3) or STIN[n]Q1C2 - 0 (bit 2 - 0), are set, the LSB or MSB of every input channel in the quadrant is forced to "1" or "0" as shown by the following table: STIN[n]Q[y]C[2:0] 0xx 100 101 110 111 Note: y = 0, 1, 2, 3 Table 12 - Quadrant Frame Bit Replacement Note that Quadrant Frame Programming and BER reception cannot be used simultaneously on the same input stream. Normal Operation Replaces LSB of every channel in Quadrant y with `0' Replaces LSB of every channel in Quadrant y with `1' Replaces MSB of every channel in Quadrant y with `0' Replaces MSB of every channel in Quadrant y with `1' Action
18.0
JTAG Port
The JTAG test port is implemented to meet the mandatory requirements of the IEEE-1149.1 (JTAG) standard. The operation of the boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.
18.1
Test Access Port (TAP)
The Test Access Port (TAP) accesses the ZL50020 test functions. It consists of three input pins and one output pin as follows: * Test Clock Input (TCK) - TCK provides the clock for the test logic. TCK does not interfere with any on-chip clock and thus remains independent in the functional mode. TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. Test Mode Selection Inputs (TMS) - The TAP Controller uses the logic signals received at the TMS input to control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to high when it is not driven from an external source. Test Data Input (TDi) - Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. The registers are described in a subsequent section. The received input data is sampled at the rising edge of the TCK pulse. This pin is internally pulled to high when it is not driven from an external source. Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or test data register are serially shifted out towards TDo. The data from TDo is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDo driver is set to a high impedance state. Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to high when it is not driven from an external source.
*
*
*
*
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Zarlink Semiconductor Inc.
ZL50020
18.2 Instruction Register
Data Sheet
The ZL50020 uses the public instructions defined in the IEEE-1149.1 standard. The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP Controller is in its shifted-OR state. These instructions are subsequently decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current and to define the serial test data register path that is used to shift data between TDi and TDo during data register scanning.
18.3
Test Data Registers
As specified in the IEEE-1149.1 standard, the ZL50020 JTAG interface contains three test data registers: * * * The Boundary-Scan Register - The Boundary-Scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the ZL50020 core logic. The Bypass Register - The Bypass register is a single stage shift register that provides a one-bit path from TDi to TDo. The Device Identification Register - The JTAG device ID for the ZL50020 is 0C36414BH Version Part Number Manufacturer ID LSB <31:28> <27:12> <11:1> <0> 0000 1100 0011 0110 0100 0001 0100 101 1
18.4
BSDL
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the IEEE-1149.1 test interface.
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Zarlink Semiconductor Inc.
ZL50020
19.0 Register Address Mapping
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W R Only R Only R Only R Only R Only R/W R/W R/W R/W R/W R/W R Only Control Register Internal Mode Selection Register Software Reset Register Output Clock and Frame Pulse Control Register Output Clock and Frame Pulse Selection Register FPo_OFF0 Register FPo_OFF1 Register FPo_OFF2 Register Internal Flag Register BER Error Flag Register 0 BER Error Flag Register 1 BER Receiver Lock Register 0 BER Receiver Lock Register 1 Stream Input Control Registers 0 - 31 Stream Input Quadrant Frame Registers 0 - 31 Stream Output Control Registers 0 - 31 BER Receiver Start Registers 0 - 31 BER Receiver Length Registers 0 - 31 BER Receiver Control Registers 0 - 31 BER Receiver Error Registers 0 - 31 Register Name Abbreviation CR IMS SRR OCFCR OCFSR FPOFF0 FPOFF1 FPOFF2 IFR BERFR0 BERFR1 BERLR0 BERLR1 SICR0 - 31 SIQFR0 - 31 SOCR0 - 31 BRSR0 - 31 BRLR0 - 31 BRCR0 - 31 BRER0 - 31
Data Sheet
Address A13 - A0 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0010H 0011H 0012H 0013H 0014H 0100H 011FH 0120H 013FH 0200H 021FH 0300H 031FH 0320H 033FH 0340H 035FH 0360H 037FH
Reset By Switch/Hardware Switch/Hardware Hardware Only Hardware Hardware Hardware Hardware Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware Switch/Hardware
Table 13 - Address Map for Registers (A13 = 0)
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Zarlink Semiconductor Inc.
ZL50020
20.0 Detailed Register Description
Data Sheet
External Read/Write Address: 0000H Reset Value: 0000H 15
0
14
0
13
0
12
0
11
OPM
10
0
9
FPIN POS
8
CKINP
7
FPINP
6
CKIN 1
5
CKIN 0
4
VAR EN
3
MBPE
2
OSB
1
MS1
0
MS0
Bit 15 - 12 11
Name Unused OPM
Description Reserved. In normal functional mode, these bits MUST be set to zero. Operation Mode. This bit is used to set the device in Master/Slave operation. Refer to Table 8, "ZL50020 Operating Modes" on page 31 for more details. Reserved. In normal functional mode, this bits MUST be set to zero. Input Frame Pulse (FPi) Position When this bit is low, FPi straddles frame boundary (as defined by ST-BUS). When this bit is high, FPi starts from frame boundary (as defined by GCI-Bus) Clock Input (CKi) Polarity When this bit is low, the CKi falling edge aligns with the frame boundary. When this bit is high, the CKi rising edge aligns with the frame boundary. Frame Pulse Input (FPi) Polarity When this bit is low, the input frame pulse FPi has the negative frame pulse format. When this bit is high, the input frame pulse FPi has the positive frame pulse format. Input Clock (CKi) and Frame Pulse (FPi) Selection
CKIN1 - 0 00 01 10 11 FPi Active Period 61 ns 122 ns 244 ns Reserved CKi 16.384 MHz 8.192 MHz 4.096 MHz
10 9
Unused FPINPOS
8
CKINP
7
FPINP
6-5
CKIN1 - 0
The MODE_4M0 and MODE_4M1 pins, as described in "Pin Description" on page 9, should also be set to define the input clock mode. 4 VAREN Variable Delay Mode Enable When this bit is low, the variable delay mode is disabled on a device-wide basis. When this bit is high, the variable delay mode is enabled on a device-wide basis. Memory Block Programming Enable When this bit is high, the connection memory block programming mode is enabled to program the connection memory. When it is low, the memory block programming mode is disabled. Table 14 - Control Register (CR) Bits
3
MBPE
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Zarlink Semiconductor Inc.
ZL50020
External Read/Write Address: 0000H Reset Value: 0000H 15
0
Data Sheet
14
0
13
0
12
0
11
OPM
10
0
9
FPIN POS
8
CKINP
7
FPINP
6
CKIN 1
5
CKIN 0
4
VAR EN
3
MBPE
2
OSB
1
MS1
0
MS0
Bit 2
Name OSB
Description Output Stand By Bit: This bit enables the STio0 - 31 and the STOHZ0 -15 serial outputs. The following table describes the HiZ control of the serial data outputs:
RESET Pin 0 1 1 1 1 SRSTSW (in SRR) X 1 0 0 0 ODE Pin X X 0 1 1 OSB Bit X X X 0 1 STio0 - 31 HiZ HiZ HiZ HiZ Active (Controlled by CM) STOHZ0 - 15 Driven High Driven High Driven High Driven High Active (Controlled by CM)
Note: Unused output streams are tristated (STio = HiZ, STOHZ = Driven High). Refer to SOCR0 - 31 (bit2 - 0). 1-0 MS1 - 0 Memory Select Bits These two bits are used to select connection memory low, connection high or data memory for access by CPU:
MS1 - 0 00 01 10 11 Memory Selection Connection Memory Low Read/Write Connection Memory High Read/Write Data Memory Read Reserved
Table 14 - Control Register (CR) Bits (continued)
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 0001H Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 STIO_ PD_EN 7 BDH 6 BDL 5 RBER EN 4 TBER EN 3 BPD 2 2 BPD 1 1 BPD 0 0 MBPS
Bit 15 - 9 8
Name Unused STIO_PD_ EN BDH
Description Reserved. In normal functional mode, these bits MUST be set to zero. STio Pull-down Enable When this bit is low, the pull-down resistors on all STio pads will be disabled. When this bit is high, the pull-down resistors on all STio pads will be enabled. Bi-directional Control for Streams 16-31
BDH 0 STio16 - 31 Operation normal operation: STi16-31 are inputs STio16-31 are outputs bi-directional operation: STi16-31 tied low internally STio16-31 are bi-directional
7
1
6
BDL
Bi-directional Control for Streams 0-15
BDL 0 STio0 - 15 Operation normal operation: STi0-15 are inputs STio0-15 are outputs bi-directional operation: STi0-15 tied low internally STio0-15 are bi-directional
1
5
RBEREN
PRBS Receiver Enable When this bit is low, all the BER receivers are disabled. To enable any BER receivers, this bit MUST be high. PRBS Transmitter Enable When this bit is low, all the BER transmitters are disabled. To enable any BER transmitters, this bit MUST be high. Table 15 - Internal Mode Selection Register (IMS) Bits
4
TBEREN
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Zarlink Semiconductor Inc.
ZL50020
External Read/Write Address: 0001H Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 STIO_ PD_EN 7 BDH 6 BDL 5 RBER EN 4 TBER EN 3 BPD 2 2 BPD 1 1
Data Sheet
0 MBPS
BPD 0
Bit 3-1
Name BPD2 - 0
Description Block Programming Data These bits refer to the value to be loaded into the connection memory, whenever the memory block programming feature is activated. After the MBPE bit in the Control Register is set to high and the MBPS bit in this register is set to high, the contents of the bits BPD2 - 0 are loaded into bits 2 - 0 of the Connection Memory Low. Bits 15 - 3 of the Connection Memory Low and bits 15 - 0 of Connection Memory High are zeroed. Memory Block Programming Start: A zero to one transition of this bit starts the memory block programming function. The MBPS and BPD2 - 0 bits in this register must be defined in the same write operation. Once the MBPE bit in the Control Register is set to high, the device requires two frames to complete the block programming. After the programming function has finished, the MBPS bit returns to low, indicating the operation is completed. When MBPS is high, MBPS or MBPE can be set to low to abort the programming operation. Whenever the microprocessor writes a one to the MBPS bit, the block programming function is started. As long as this bit is high, the user must maintain the same logical value to the other bits in this register to avoid any change in the device setting.
0
MBPS
Table 15 - Internal Mode Selection Register (IMS) Bits (continued)
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Zarlink Semiconductor Inc.
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External Read/Write Address: 0002H Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 SRST SW
Data Sheet
0 0
Bit 15 - 2 1
Name Unused SRSTSW
Description Reserved In normal functional mode, these bits MUST be set to zero. Software Reset Bit for Switch When this bit is low, switching blocks are in normal operation. When this bit is high, switching blocks are in software reset state. Refer to Table 12, "Address Map for Registers (A13 = 0)" on page 32 for details regarding which registers are affected. Reserved In normal functional mode, these bits MUST be set to zero. Table 16 - Software Reset Register (SRR) Bits
0
Unused
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 0003H Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 FPOF2 EN 7 FPOF1 EN 6 FPOF0 EN 5 0 4 0 3 CKO FPO3 EN 2 CKO FPO2 EN 1 CKO FPO1 EN 0 CKO FPO0 EN
Bit 15 - 9 8
Name Unused FPOF2EN
Description Reserved In normal functional mode, these bits MUST be set to zero. FPo_OFF2 Enable When this bit is high, output frame pulse FPo_OFF2 When this bit is low, output frame pulse FPo_OFF2. FPo_OFF1 Enable When this bit is high, output frame pulse FPo_OFF1 is enabled. When this bit is low, output frame pulse FPo_OFF1 is in high impedance state. FPo_OFF0 Enable When this bit is high, output frame pulse FPo_OFF0 is enabled. When this bit is low, output frame pulse FPo_OFF0 is in high impedance state. Reserved In normal functional mode, these bits MUST be set to zero. Reserved In normal functional mode, these bits MUST be set to zero. CKo3 and FPo3 Enable When this bit is high, output clock CKo3 and output frame pulse FPo3 are enabled. When this bit is low, CKo3 and FPo3 are in high impedance state. CKo2 and FPo2 Enable When this bit is high, output clock CKo2 and output frame pulse FPo2 are enabled. When this bit is low, CKo2 and FPo2 are in high impedance state. CKo1 and FPo1 Enable When this bit is high, output clock CKo1 and output frame pulse FPo1 are enabled. When this bit is low, CKo1 and FPo1 are in high impedance state. CKo0 and FPo0 Enable When this bit is high, output clock CKo0 and output frame pulse FPo0 are enabled. When this bit is low, CKo0 and FPo0 are in high impedance state.
7
FPOF1EN
6
FPOF0EN
5 4 3
Unused Unused CKOFPO3 EN CKOFPO2 EN CKOFPO1 EN CKOFPO0 EN
2
1
0
Table 17 - Output Clock and Frame Pulse Control Register (OCFCR) Bits
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 0004H Reset Value: 0000H
15 0 14 0 13 CKO FPO3 SEL1 12 CKO FPO3 SEL0 11 CKO3 P 10 FPO3 P 9 FPO3 POS 8 CKO2 P 7 FPO2 P 6 FPO2 POS 5 CKO1 P 4 FPO1 P 3 FPO1 POS 2 CKO0 P 1 FPO0 P 0 FPO0 POS
Bit 15 - 14 13 - 12
Name Unused CKOFPO3 SEL1 - 0
Description Reserved In normal functional mode, these bits MUST be set to zero. Output Clock (CKo3) Frequency and Output Frame Pulse (FPo3) Pulse Cycle Selection
CKOFPO3 SEL1 - 0 00 01 10 11 FPo3 244 ns 122 ns 61 ns 30 ns CKo3 4.096 MHz 8.192 MHz 16.384 MHz 32.768 MHz
11
CKO3P
Output Clock (CKo3) Polarity Selection When this bit is low, the output clock CKo3 falling edge aligns with the frame boundary. When this bit is high, the output clock CKo3 rising edge aligns with the frame boundary. Output Frame Pulse (FPo3) Polarity Selection When this bit is low, the output frame pulse FPo3 has the negative frame pulse format. When this bit is high, the output frame pulse FPo3 has the positive frame pulse format. Output Frame Pulse (FPo3) Position When this bit is low, FPo3 straddles frame boundary (as defined by ST-BUS). When this bit is high, FPo3 starts from frame boundary (as defined by GCI-Bus). Output Clock (CKo2) Polarity Selection When this bit is low, the output clock CKo2 falling edge aligns with the frame boundary. When this bit is high, the output clock CKo2 rising edge aligns with the frame boundary. Output Frame Pulse (FPo2) Polarity Selection When this bit is low, the output frame pulse FPo2 has the negative frame pulse format. When this bit is high, the output frame pulse FPo2 has the positive frame pulse format. Output Frame Pulse (FPo2) Position When this bit is low, FPo2 straddles frame boundary (as defined by ST-BUS). When this bit is high, FPo2 starts from frame boundary (as defined by GCI-Bus).
10
FPO3P
9
FPO3POS
8
CKO2P
7
FPO2P
6
FPO2POS
Table 18 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits
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Zarlink Semiconductor Inc.
ZL50020
External Read/Write Address: 0004H Reset Value: 0000H
15 0 14 0 13 CKO FPO3 SEL1 12 CKO FPO3 SEL0 11 CKO3 P 10 FPO3 P 9 FPO3 POS 8 CKO2 P 7 FPO2 P 6 FPO2 POS 5 CKO1 P 4 FPO1 P 3 FPO1 POS 2 CKO0 P
Data Sheet
1 FPO0 P
0 FPO0 POS
Bit 5
Name CKO1P
Description Output Clock (CKo1) Polarity Selection When this bit is low, the output clock CKo1 falling edge aligns with the frame boundary. When this bit is high, the output clock CKo1 rising edge aligns with the frame boundary. Output Frame Pulse (FPo1) Polarity Selection When this bit is low, the output frame pulse FPo1 has the negative frame pulse format. When this bit is high, the output frame pulse FPo1 has the positive frame pulse format. Output Frame Pulse (FPo1) Position When this bit is low, FPo1 straddles frame boundary (as defined by ST-BUS). When this bit is high, FPo1 starts from frame boundary (as defined by GCI-Bus). Output Clock (CKo0) Polarity Selection When this bit is low, the output clock CKo0 falling edge aligns with the frame boundary. When this bit is high, the output clock CKo0 rising edge aligns with the frame boundary. Output Frame Pulse (FPo0) Polarity Selection When this bit is low, the output frame pulse FPo0 has the negative frame pulse format. When this bit is high, the output frame pulse FPo0 has the positive frame pulse format. Output Frame Pulse (FPo0) Position When this bit is low, FPo0 straddles frame boundary (as defined by ST-BUS). When this bit is high, FPo0 starts from frame boundary (as defined by GCI-Bus).
4
FPO1P
3
FPO1POS
2
CKO0P
1
FPO0P
0
FPO0POS
Note: In Divided Clock modes, CKo3 - 1 cannot exceed frequency of CKi.
Table 18 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits (continued)
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Zarlink Semiconductor Inc.
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Data Sheet
External Read/Write Address: 0005H - 0007H Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 FOF[n] OFF7 8 FOF[n] OFF6 7 FOF[n] OFF5 6 FOF[n] OFF4 5 FOF[n] OFF3 4 FOF[n] OFF2 3 FOF[n] OFF1 2 FOF[n] OFF0 1 FOF[n] C1 0 FOF[n] C0
Bit 15 - 10 9-2
Name Unused
FOF[n]OFF7 - 0
Description Reserved. In normal functional mode, these bits MUST be set to zero. FPo_OFF[n] Channel Offset The binary value of these bits refers to the channel offset from original frame boundary. Permitted channel offset values depend on bits 1-0 of this register. FPo_OFF[n] Control bits
FOF[n]C 1-0 00 01 10 11 Data Rate (Mbps) 2.048 4.096 8.192 16.384 FPo_OFF[n] Pulse Cycle Width one 4.096 MHz clock one 8.192 MHz clock one 16.384 MHz clock one 16.384 MHz clock FOF[n]OFF7 - 0 Permitted Channel Offset 0 - 31 0 - 63 0 - 127 0 - 255 Polarity Control FPO0P FPO1P FPO2P FPO2P Position Control FPO0POS FPO1POS FPO2POS FPO2POS
1-0
FOF[n]C1 - 0
Note: [n] denotes output offset frame pulse from 0 to 2.
Table 19 - FPo_OFF[n] Register (FPo_OFF[n]) Bits
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Zarlink Semiconductor Inc.
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Data Sheet
External Read Address: 0010H Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 OUT ERR 0 IN ERR
Bit 15 - 2 1
Name Unused OUTERR
Description Reserved In normal functional mode, these bits are zero. Output Error (Read Only) This bit is set high when the total number of output channels is programmed to be more than the maximum capacity of 2048, in which case the output channels beyond the maximum capacity should be disabled. This bit will be cleared automatically after programming is corrected. Input Error (Read Only) This bit is set high when the total number of input channels is programmed to be more than the maximum capacity of 2048, in which case the input channels beyond the maximum capacity should be disabled.This bit will be cleared automatically after programming is corrected. Table 20 - Internal Flag Register (IFR) Bits - Read Only
0
INERR
External Read Address: 00011H Reset Value: 0000H
15 BER F15 14 BER F14 13 BER F13 12 BER F12 11 BER F11 10 BER F10 9 BER F9 8 BER F8 7 BER F7 6 BER F6 5 BER F5 4 BER F4 3 BER F3 2 BER F2 1 BER F1 0 BER F0
Bit 15 - 0
Name BERF[n]
Description BER Error Flag[n]: If BERF[n] is high, it indicates that BER Receiver Error Register [n] (BRER[n]) is not zero. If BERF[n] is low, it indicates that BER Receiver Error Register [n] (BRER[n]) is zero.
Note: [n] denotes input stream from 0 - 15.
Table 21 - BER Error Flag Register 0 (BERFR0) BIts - Read Only
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Zarlink Semiconductor Inc.
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Data Sheet
External Read/Write Address: 00012H Reset Value: 0000H
15 BER F31 14 BER F30 13 BER F29 12 BER F28 11 BER F27 10 BER F26 9 BER F25 8 BER F24 7 BER F23 6 BER F22 5 BER F21 4 BER F20 3 BER F19 2 BER F18 1 BER F17 0 BER F16
Bit 15 - 0
Name BERF[n]
Description BER Error Flag[n]: If BERF[n] is high, it indicates that BER Receiver Error Register [n] (BRER[n]) is not zero. If BERF[n] is low, it indicates that BER Receiver Error Register [n] (BRER[n]) is zero.
Note: [n] denotes input stream from 16 - 31.
Table 22 - BER Error Flag Register 1 (BERFR1) Bits - Read Only
External Read Address: 00013H Reset Value: 0000H
15 BER L15 14 BER L14 13 BER L13 12 BER L12 11 BER L11 10 BER L10 9 BER L9 8 BER L8 7 BER L7 6 BER L6 5 BER L5 4 BER L4 3 BER L3 2 BER L2 1 BER L1 0 BER L0
Bit 15 - 0
Name BERL[n]
Description BER Receiver Lock[n] If BERL[n] is high, it indicates that BER Receiver of STi[n] is locked. If BERL[n] is low, it indicates that BER Receiver of STi[n] is not locked.
Note: [n] denotes input stream from 0 - 15.
Table 23 - BER Receiver Lock Register 0 (BERLR0) Bits - Read Only
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Zarlink Semiconductor Inc.
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Data Sheet
External Read Address: 00014H Reset Value: 0000H
15 BER L31 14 BER L30 13 BER L29 12 BER L28 11 BER L27 10 BER L26 9 BER L25 8 BER L24 7 BER L23 6 BER L22 5 BER L21 4 BER L20 3 BER L19 2 BER L18 1 BER L17 0 BER L16
Bit 15 - 0
Name BERL[n]
Description BER Receiver Lock[n]: If BERL[n] is high, it indicates that BER Receiver of STi[n] is locked. If BERL[n] is low, it indicates that BER Receiver of STi[n] is not locked.
Note: [n] denotes input stream from 16 - 31.
Table 24 - BER Receiver Lock Register 1 (BERLR1) Bits - Read Only
External Read/Write Address: 0100H - 011FH Reset Value: 0000H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
0
0
0
0
0
STIN[n] BD2
STIN[n] BD1
STIN[n] BD0
STIN[n] SMP1
STIN[n] SMP0
STIN[n] DR3
STIN[n] DR2
STIN[n] DR1
STIN[n] DR0
Bit
15 - 9 8-6
Name Unused STIN[n]BD2 - 0
Description Reserved In normal functional mode, these bits MUST be set to zero. Input Stream[n] Bit Delay Bits. The binary value of these bits refers to the number of bits that the input stream will be delayed relative to FPi. The maximum value is 7. Zero means no delay. Input Data Sampling Point Selection Bits
STIN[n]SMP1-0 00 01 10 11 Sampling Point (2.048 Mbps, 4.096 Mbps, 8.192 Mbps streams) 3/4 point 1/4 point 2/4 point 4/4 point 4/4 point Sampling Point (16.384 Mbps streams) 2/4 point
5-4
STIN[n]SMP1 - 0
Table 25 - Stream Input Control Register 0 - 31 (SICR0 - 31) Bits
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Zarlink Semiconductor Inc.
ZL50020
External Read/Write Address: 0100H - 011FH Reset Value: 0000H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Data Sheet
0
0
0
0
0
0
0
0
STIN[n] BD2
STIN[n] BD1
STIN[n] BD0
STIN[n] SMP1
STIN[n] SMP0
STIN[n] DR3
STIN[n] DR2
STIN[n] DR1
STIN[n] DR0
Bit 3-0
Name STIN[n]DR3 - 0 Input Data Rate Selection Bits:
STIN[n]DR3-0 0000 0001 0010 0011 0100 0101 - 1111
Description
Data Rate Stream Unused 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps Reserved
Note: [n] denotes input stream from 0 - 31.
Table 25 - Stream Input Control Register 0 - 31 (SICR0 - 31) Bits (continued)
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Zarlink Semiconductor Inc.
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Data Sheet
External Read/Write Address: 0120H - 013FH Reset Value: 0000H
15 14 13 12 11 STIN[n] Q3C2 10 STIN[n] Q3C1 9 STIN[n] Q3C0 8 STIN[n] Q2C2 7 STIN[n] Q2C1 6 STIN[n] Q2C0 5 STIN[n] Q1C2 4 STIN[n] Q1C1 3 STIN[n] Q1C0 2 STIN[n] Q0C2 1 STIN[n] Q0C1 0 STIN[n] Q0C0
0
0
0
0
Bit 15 - 12 11 - 9
Name Unused STIN[n]Q3C2 - 0
Description Reserved In normal functional mode, these bits MUST be set to zero. Quadrant Frame 3 Control Bits These three bits are used to control STi[n]'s quadrant frame 3, which is defined as Ch24 to 31, Ch48 to 63, Ch96 to 127 and Ch192 to 255 for the 2.048 Mbps, 4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q3C 2-0 0xx 100 101 110 111 Operation normal operation LSB of each channel is replaced by "0" LSB of each channel is replaced by "1" MSB of each channel is replaced by "0" MSB of each channel is replaced by "1"
8-6
STIN[n]Q2C2 - 0
Quadrant Frame 2 Control Bits These three bits are used to control STi[n]'s quadrant frame 2, which is defined as Ch16 to 23, Ch32 to 47, Ch64 to 95 and Ch128 to 191 for the 2.048 Mbps, 4.096 Mbps 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q2C 2-0 0xx 100 101 110 111 Operation normal operation LSB of each channel is replaced by "0" LSB of each channel is replaced by "1" MSB of each channel is replaced by "0" MSB of each channel is replaced by "1"
Table 26 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits
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Zarlink Semiconductor Inc.
ZL50020
External Read/Write Address: 0120H - 013FH Reset Value: 0000H
15 14 13 12 11 STIN[n] Q3C2 10 STIN[n] Q3C1 9 STIN[n] Q3C0 8 STIN[n] Q2C2 7 STIN[n] Q2C1 6 STIN[n] Q2C0 5 STIN[n] Q1C2 4 STIN[n] Q1C1 3 STIN[n] Q1C0 2 STIN[n] Q0C2 1
Data Sheet
0 STIN[n] Q0C0
0
0
0
0
STIN[n] Q0C1
Bit 5-3
Name STIN[n]Q1C2 - 0
Description Quadrant Frame 1 Control Bits these three bits are used to control STi[n]'s quadrant frame 1, which is defined as Ch8 to 15, Ch16 to 31, Ch32 to 63 and Ch64 to 127 for the 2.048 Mbps, 4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q1C 2-0 0xx 100 101 110 111 Operation normal operation LSB of each channel is replaced by "0" LSB of each channel is replaced by "1" MSB of each channel is replaced by "0" MSB of each channel is replaced by "1"
2-0
STIN[n]Q0C2 - 0
Quadrant Frame 0 Control Bits These three bits are used to control STi[n]'s quadrant frame 0, which is defined as Ch0 to 7, Ch0 to 15, Ch0 to 31 and Ch0 to 63 for the 2.048 Mbps, 4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q0C2-0 0xx 100 101 110 111 Operation normal operation LSB of each channel is replaced by "0" LSB of each channel is replaced by "1" MSB of each channel is replaced by "0" MSB of each channel is replaced by "1"
Note: [n] denotes input stream from 0 - 31.
Table 26 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits (continued)
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Zarlink Semiconductor Inc.
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Data Sheet
External Read/Write Address: 0200H - 021FH Reset Value: 0000H
15 14 13 12 11 STOHZ [n]A2 10 STOHZ [n]A1 9 STOHZ [n]A0 8 STO[n] FA1 7 STO[n] FA0 6 STO[n] AD2 5 STO[n] AD1 4 STO[n] AD0 3 STO[n] DR3 2 STO[n] DR2 1 STO[n] DR1 0 STO[n] DR0
0
0
0
0
Bit 15 - 12 11 - 9
Name Unused STOHZ[n]A2 - 0
(Valid only for STio0-15)
Description Reserved In normal functional mode, these bits MUST be set to zero. STOHZ Additional Advancement Bits
STOHZ[n]A2-0 000 001 010 011 100 101-111 Additional Advancement (2.048 Mbps, 4.096 Mbps, 8.192 Mbps) 0 bit 1/4 bit 2/4 bit 3/4 bit 4/4 bit Reserved Additional Advancement (16.384 Mbps streams) 0 bit 2/4 bit 4/4 bit Reserved
8-7
STO[n]FA1 - 0
Output Stream[n] Fractional Advancement Bits
STO[n]FA1-0 00 01 10 11 Advancement (2.048 Mbps, 4.096 Mbps, 8.192 Mbps streams) 0 1/4 bit 2/4 bit 3/4 bit Advancement (16.384 Mbps streams) 0 2/4 Reserved
6-4
STO[n]AD2 - 0
Output Stream[n] Bit Advancement Selection Bits The binary value of these bits refers to the number of bits that the output stream is to be advanced relative to FPo. The maximum value is 7. Zero means no advancement. Output Data Rate Selection Bits
STIN[n]DR3 - 0 0000 0001 0010 0011 0100 0101 - 1111 Data Rate disabled: STio HiZ (STOHZ driven high) 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps Reserved
3-0
STO[n]DR3 - 0
Note: [n] denotes output stream from 0 - 31.
Table 27 - Stream Output Control Register 0 - 31 (SOCR0 - 31) Bits
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
External Read/Write Address: 0300H - 031FH Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 ST[n] BRS7 6 ST[n] BRS6 5 ST[n] BRS5 4 ST[n] BRS4 3 ST[n] BRS3 2 ST[n] BRS2 1 ST[n] BRS1 0 ST[n] BRS0
Bit 15 - 8 7-0
Name Unused ST[n] BRS7 - 0
Description Reserved In normal functional mode, these bits MUST be set to zero. Stream[n] BER Receive Start Bits The binary value of these bits refers to the input channel in which the BER data starts to be compared.
Note: [n] denotes input stream from 0 - 31.
Table 28 - BER Receiver Start Register [n] (BRSR[n]) Bits
External Read/Write Address: 0320H - 03FH Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 ST[n] BL8 7 ST[n] BL7 6 ST[n] BL6 5 ST[n] BL5 4 ST[n] BL4 3 ST[n] BL3 2 ST[n] BL2 1 ST[n] BL1 0 ST[n] BL0
Bit 15 - 9 8-0
Name Unused ST[n] BL8 - 0
Description Reserved In normal functional mode, these bits MUST be set to zero. Stream[n] BER Length Bits The binary value of these bits refers to the number of consecutive channels expected to receive the BER pattern. The maximum number of BER channels is 32, 64, 128 and 256 for the data rates of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps respectively. The minimum number of BER channels is 1. If these bits are set to zero, no BER test will be performed.
Note: [n] denotes input stream from 0 - 31.
Table 29 - BER Receiver Length Register [n] (BRLR[n]) Bits
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Zarlink Semiconductor Inc.
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Data Sheet
External Read/Write Address: 0340H - 035FH Reset Value: 0000H
15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 ST[n] CBER 0 ST[n] SBER
Bit 15 - 2 1
Name Unused ST[n] CBER ST[n] SBER
Description Reserved In normal functional mode, these bits MUST be set to zero. Stream[n] Bit Error Rate Counter Clear When this bit is high, it resets the internal bit error counter and the stream BER Receiver Error Register to zero. Stream[n] Bit Error Rate Test Start When this bit is high, it enables the BER receiver; starts the bit error rate test. The bit error test result is kept in the BER Receiver Error (BRER[n]) register. Upon the completion of the BER test, set this bit to zero. Note that the RBEREB bit must be set in the IMS Register first.
0
Note: [n] denotes input stream from 0 - 31
Table 30 - BER Receiver Control Register [n] (BRCR[n]) Bits
External Read Address: 0360H - 037FH Reset Value: 0000H
15 ST[n] BC15 14 ST[n] BC14 13 ST[n] BC13 12 ST[n] BC12 11 ST[n] BC11 10 ST[n] BC10 9 ST[n] BC9 8 ST[n] BC8 7 ST[n] BC7 6 ST[n] BC6 5 ST[n] BC5 4 ST[n] BC4 3 ST[n] BC3 2 ST[n] BC2 1 ST[n] BC1 0 ST[n] BC0
Bit 15 - 0
Name ST[n] BC15 - 0
Description Stream[n] BER Count Bits (Read Only) The binary value of these bits refers to the bit error counts. When it reaches its maximum value of 0xFFFF, the value will be held and will not rollover.
Note: [n] denotes input stream from 0 - 31
Table 31 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only
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Zarlink Semiconductor Inc.
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21.0
21.1
Data Sheet
Memory
Memory Address Mappings
When A13 is high, the data or connection memory can be accessed by the microprocessor port. Bit 1 - 0 in the Control Register determine the access to the data or connection memory (CM_L or CM_H).
MSB (Note 1) Stream Address (St0 - 31) A12 0 0 0 0 0 0 0 0 0 . . . . . 0 0 . . . . 1 1 A11 0 0 0 0 0 0 0 0 1 . . . . . 1 1 . . . . 1 1 A10 0 0 0 0 1 1 1 1 0 . . . . . 1 1 . . . . 1 1 A9 0 0 1 1 0 0 1 1 0 . . . . . 1 1 . . . . 1 1 A8 0 1 0 1 0 1 0 1 0 . . . . . 0 1 Stream [n] Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7 Stream 8 . . . . . Stream 14 Stream 15 . . . . Stream 30 Stream 31 A7 0 0 . . 0 0 0 0 . . 0 0 . . . . 0 0 . . . . 1 1 A6 0 0 . . 0 0 0 0 . . 0 0 . . . . 1 1 . . . . 1 1 A5 0 0 . . 0 0 1 1 . . 1 1 . . . . 1 1 . . . . 1 1 A4 0 0 . . 1 1 0 0 1 1 . . . . 1 1 . . . . 1 1 Channel Address (Ch0 - 255) A3 0 0 . . 1 1 0 0 . . 1 1 . . . . 1 1 . . . . 1 1 A2 0 0 . . 1 1 0 0 . 1 1 . . . . 1 1 . . . . 1 1 A1 0 0 . . 1 1 0 0 1 1 . . . . 1 1 . . . . 1 1 A0 0 1 . . 0 1 0 1 . . 0 1 . . . . 0 1 . . . . 0 1 Channel [n] Ch 0 Ch 1 . . Ch 30 Ch 31 (Note 2) Ch 32 Ch 33 . . Ch 62 Ch 63 (Note 3) . . . . Ch126 Ch 127 (Note 4) . . . . Ch 254 Ch 255 (Note 5)
A13
1 1 1 1 1 1 1 1 1 . . . . . 1 1 . . . . 1 1
Notes: 1. A13 must 2. Channels 3. Channels 4. Channels 5. Channels
be high for access to data and connection memory positions. A13 must be low to access internal registers. 0 to 31 are used when serial stream is at 2.048 Mbps. 0 to 63 are used when serial stream is at 4.096 Mbps. 0 to 127 are used when serial stream is at 8.192 Mbps. 0 to 255 are used when serial stream is at 16.384 Mbps.
Table 32 - Address Map for Memory Locations (A13 = 1)
21.2
Connection Memory Low (CM_L) Bit Assignment
When the CMM bit (bit 0) in the connection memory low is zero, the per-channel transmission is set to the normal channel-switching. The connection memory low bit assignment for the channel transmission mode is shown in Table 33 on page 56.
15
UA EN
14
V/C
13
SSA 4
12
SSA 3
11
SSA 2
10
SSA 1
9
SSA 0
8
SCA 7
7
SCA 6
6
SCA 5
5
SCA 4
4
SCA 3
3
SCA 2
2
SCA 1
1
SCA 0
0
CMM =0
Bit 15
Name UAEN
Description Conversion between -law and A-law Enable When this bit is low, normal switch without -law/A-law conversion. Connection memory high will be ignored. When this bit is high, switch with -law/A-law conversion, and connection memory high controls the conversion method.
Table 33 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
15
UA EN
14
V/C
13
SSA 4
12
SSA 3
11
SSA 2
10
SSA 1
9
SSA 0
8
SCA 7
7
SCA 6
6
SCA 5
5
SCA 4
4
SCA 3
3
SCA 2
2
SCA 1
1
SCA 0
0
CMM =0
Bit 14
Name V/C
Description Variable/Constant Delay Control When this bit is low, the output data for this channel will be taken from constant delay memory. When this bit is set to high, the output data for this channel will be taken from variable delay memory. Note that VAREN must be set in Control Register first. Source Stream Address The binary value of these 5 bits represents the input stream number. Source Channel Address The binary value of these 8 bits represents the input channel number. Connection Memory Mode = 0 If this is low, the connection memory is in the normal switching mode. Bit13 1 are the source stream number and channel number.
13 - 9 8-1 0
SSA4 - 0 SCA7 - 0 CMM = 0
Note: For proper -law/A-law conversion, the CM_H bits should be set before Bit 15 (UAEN bit) is set to high.
Table 33 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0 When CMM is one, the device is programmed to perform one of the special per-channel transmission modes. Bits PCC0 and PCC1 from connection memory are used to select the per-channel tristate, message or BER test mode as shown in Table 34 on page 57.
15
UA EN
14
0
13
0
12
0
11
0
10
MSG 7
9
MSG 6
8
MSG 5
7
MSG 4
6
MSG 3
5
MSG 2
4
MSG 1
3
MSG 0
2
PCC 1
1
PCC 0
0
CMM =1
Bit 15
Name UAEN
Description Conversion between -law and A-law Enable (Message mode only) When this bit is low, message mode has no -law/A-law conversion. Connection memory high will be ignored. When this bit is high, message mode has -law/A-law conversion, and connection memory high controls the conversion method. Reserved In normal functional mode, these bits MUST be set to zero. Message Data Bits 8-bit data for the message mode. Not used in the per-channel tristate and BER test modes.
14 - 11 10 - 3
Unused MSG7 - 0
Table 34 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
15
UA EN
14
0
13
0
12
0
11
0
10
MSG 7
9
MSG 6
8
MSG 5
7
MSG 4
6
MSG 3
5
MSG 2
4
MSG 1
3
MSG 0
2
PCC 1
1
PCC 0
0
CMM =1
Bit 2-1
Name PCC1 - 0
Description Per-Channel Control Bits These two bits control the corresponding entry's value on the STio stream.
PC C1 0 0 1 1 PC C0 0 1 0 1 Channel Output Mode Per Channel Tristate Message Mode BER Test Mode Reserved
0
CMM = 1
Connection Memory Mode = 1 If this is high, the connection memory is in the per-channel control mode which is per-channel tristate, per-channel message mode or per-channel BER mode.
Note: For proper -law/A-law conversion, the CM_H bits should be set before Bit 15 (UAEN bit) is set to high.
Table 34 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1
21.3
Connection Memory High (CM_H) Bit Assignment
Connection memory high provides the detailed information required for -law and A-law conversion. ICL and OCL bits describe the Input Coding Law and the Output Coding Law, respectively. They are used to select the expected PCM coding laws for the connection, on the TDM inputs, and on the TDM outputs. The V/D bit is used to select the class of coding law. If the V/D bit is cleared (to select a voice connection), the ICL and OCL bits select between A-law and -law specifications related to G.711 voice coding. If the V/D bit is set (to select a data connection), the ICL and OCL bits select between various bit inverting protocols. These coding laws are illustrated in the following table. If the ICL is different than the OCL, all data bytes passing through the switch on that particular connection are translated between the indicated laws. If the ICL and the OCL are the same, no coding law translation is performed. The ICL, the OCL bits and V/D bit only have an effect on PCM code translations for constant delay connections, variable delay connections and per-channel message mode.
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
V/D
3
ICL 1
2
ICL 0
1
OCL 1
0
OCL 0
Bit
Name
Description
15 - 5
Unused
Reserved In normal functional mode, these bits MUST be set to zero.
Table 35 - Connection Memory High (CM_H) Bit Assignment
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
V/D
3
ICL 1
2
ICL 0
1
OCL 1
0
OCL 0
Bit
Name
Description
4
V/D
Voice/Data Control When this bit is low, the corresponding channel is for voice. When this bit is high, the corresponding channel is for data. Input Coding Law.
ICL1-0 00 01 10 11 Input Coding Law For Voice (V/D bit = 0) CCITT.ITU A-law CCITT.ITU -law A-law w/o ABI -law w/o Magnitude Inversion For Data (V/D bit = 1) No code ABI Inverted ABI All Bits Inverted
3-2
ICL1 - 0
1-0
OCL1 - 0
Output Coding Law
OCL1-0 00 01 10 11 Output Coding Law For Voice (V/D bit = 0) CCITT.ITU A-law CCITT.ITU -law A-law w/o ABI -law w/o Magnitude Inversion For Data (V/D bit = 1) No code ABI Inverted ABI All Bits Inverted
Note 1: Note 2:
For proper -law/A-law conversion, the CM_H bits should be set before Bit 15 of CM_L is set to high. Refer to G.711 standard for detail information of different laws.
Table 35 - Connection Memory High (CM_H) Bit Assignment
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Zarlink Semiconductor Inc.
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22.0 DC Parameters
Data Sheet
Absolute Maximum Ratings* Parameter 1 2 3 4 5 6 7 I/O Supply Voltage Core Supply Voltage Input Voltage Input Voltage (5 V-tolerant inputs) Continuous Current at Digital Outputs Package Power Dissipation Storage Temperature Symbol VDD_IO VDD_CORE VI_3V VI_5V Io PD TS - 55 Min. -0.5 -0.5 -0.5 -0.5 Max. 5.0 2.5 VDD + 0.5 7.0 15 1.5 +125 Units V V V V mA W C
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 5 Operating Temperature Positive Supply Positive Supply Input Voltage Input Voltage on 5 V-Tolerant Inputs Sym. TOP VDD_IO VDD_CORE VI VI_5V Min. -40 3.0 1.71 0 0 Typ. 25 3.3 1.8 3.3 5.0 Max. +85 3.6 1.89 VDD_IO 5.5 Units C V V V V
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics 1 2 3 4 5 6 7 8 9 Supply Current - VDD_CORE Supply Current - VDD_IO Input High Voltage Input Low Voltage Input Leakage (input pins) Input Leakage (bi-directional pins) Weak Pullup Current Weak Pulldown Current Input Pin Capacitance Output High Voltage Sym. IDD_CORE IDD_IO VIH VIL IIL IBL IPU IPD CI VOH VOL IOZ CO 5 2.4 0.4 5 10 -33 33 3 2.0 0.8 5 5 Min. Typ. Max. 120 70 Units mA mA V V A A A A pF V V A pF IOH = 8 mA IOL = 8 mA 0 < V < VDD 010 Output Low Voltage 11 Output High Impedance Leakage 12 Output Pin Capacitance
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing. Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (VIN).
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Zarlink Semiconductor Inc.
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23.0 AC Parameters
Data Sheet
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels Characteristics 1 2 CMOS Threshold Rise/Fall Threshold Voltage High Sym. VCT VHM Level 0.5 VDD_IO 0.7 VDD_IO Units V V V Conditions
3 Rise/Fall Threshold Voltage Low VLM 0.3 VDD_IO Characteristics are over recommended operating conditions unless otherwise stated.
Timing Reference Points ALL SIGNALS V HM V CT V LM
Figure 19 - Timing Parameter Measurement Voltage Levels
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Zarlink Semiconductor Inc.
ZL50020
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode - Read Access Characteristics 1 2 3 4 5 6 7 8 9 CS de-asserted time DS de-asserted time CS setup to DS falling R/W setup to DS falling Address setup to DS falling CS hold after DS rising R/W hold after DS rising Address hold after DS rising Data setup to DTA Low Sym. tCSD tDSD tCSS tRWS tAS tCSH tRWH tAH tDS tDHZ tAKD 75 185 tAKH tAKZ 4 12 8 ns ns ns ns Min. 15 15 0 10 5 0 0 0 8 7 Typ. Max. Units ns ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions2
CL = 50 pF CL = 50 pF, RL = 1 K (Note 1)
10 Data hold after DS rising 11 Acknowledgement delay time. From DS low to DTA low: Registers Memory 12 Acknowledgement hold time. From DS high to DTA high 13 DTA drive high to HiZ
Note 1: Note 2:
CL = 50 pF CL = 50 pF CL = 50 pF, RL = 1 K (Note 1)
High impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L . A delay of 500 s to 2 ms (see Section 14.2 on page 32) must be applied before the first microprocessor access is performed after the RESET pin is set high.
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tCSD tCSS tCSH
CS
tDSD
VCT
DS R/W
VCT
tRWS
tRWH
VCT
tAS tAH
VALID ADDRESS
A0-A13
VCT
tDHZ
D0-D15
tDS
VALID READ DATA
VCT
tAKZ
DTA
tAKD
VCT
tAKH
Figure 20 - Motorola Non-Multiplexed Bus Timing - Read Access
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Zarlink Semiconductor Inc.
ZL50020
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode - Write Access Characteristics 1 2 3 4 5 6 7 8 9 CS de-asserted time DS de-asserted time CS setup to DS falling R/W setup to DS falling Address setup to DS falling Data setup to DS falling CS hold after DS rising R/W hold after DS rising Address hold after DS rising Sym. tCSD tDSD tCSS tRWS tAS tDS tCSH tRWH tAH tDH tAKD 55 150 tAKH tAKZ 4 12 8 ns ns ns ns Min. 15 15 0 10 5 0 0 0 0 5 Typ. Max. Units ns ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions2
CL = 50 pF
10 Data hold from DS rising 11 Acknowledgement delay time. From DS low to DTA low: Registers Memory 12 Acknowledgement hold time. From DS high to DTA high 13 DTA drive high to HiZ
Note 1: Note 2:
CL = 50 pF, RL = 1 K (Note 1)
CL = 50 pF CL = 50 pF CL = 50 pF, RL = 1 K (Note 1)
High impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L . A delay of 500 s to 2 ms (see Section 14.2 on page 32) must be applied before the first microprocessor access is performed after the RESET pin is set high.
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tCSD tCSH
tCSS
CS
tDSD
VCT
DS R/W
VCT
tRWS tRWH
VCT
tAS tAH
VALID ADDRESS
A0-A13
tDS
VCT
tDH
D0-D15
VALID WRITE DATA
VCT
tAKZ
DTA
tAKD
VCT
tAKH
Figure 21 - Motorola Non-Multiplexed Bus Timing - Write Access
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Zarlink Semiconductor Inc.
ZL50020
AC Electrical Characteristics - Intel Non-Multiplexed Bus Mode - Read Access Characteristics 1 2 3 4 5 6 7 8 9 CS de-asserted time RD setup to CS falling WR setup to CS falling Address setup to CS falling RD hold after CS rising WR hold after CS rising Address hold after CS rising Data setup to RDY high Data hold after CS rising Sym. tCSD tRS tWS tAS tRH tWH tAH tDS tCSZ tAKD 175 185 tAKH tAKZ 4 12 8 ns ns ns ns Min. 15 10 10 5 0 0 0 8 7 Typ. Max. Units ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions2
CL = 50 pF CL = 50 pF, RL = 1 K (Note 1)
10 Acknowledgement delay time. From CS low to RDY high: Registers Memory 11 Acknowledgement hold time. From CS high to RDY low 12 RDY drive low to HiZ
Note 1: Note 2:
CL = 50 pF CL = 50 pF CL = 50 pF, RL = 1 K (Note 1)
High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge C L . A delay of 500 s to 2 ms (see Section 14.2 on page 32) must be applied before the first microprocessor access is performed after the RESET pin is set high.
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tCSD
CS
tRS tRH
VCT
RD
tWS tWH
VCT
WR
tAS tAH
VALID ADDRESS
VCT
A0-A13
VCT
tCSZ
D0-D15
tDS
VALID READ DATA
VCT
tAKZ
RDY
tAKD tAKH
VCT
Figure 22 - Intel Non-Multiplexed Bus Timing - Read Access
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Zarlink Semiconductor Inc.
ZL50020
AC Electrical Characteristics - Intel Non-Multiplexed Bus Mode - Write Access Characteristics 1 2 3 4 5 6 7 8 9 CS de-asserted time WR setup to CS falling RD setup to CS falling Address setup to CS falling Data setup to CS falling WR hold after CS rising RD hold after CS rising Address hold after CS rising Data hold after CS rising Sym. tCSD tWS tRS tAS tDS tWH tRH tAH tDH tAKD 55 150 tAKH tAKZ 4 12 8 ns ns ns ns Min. 15 10 10 5 0 0 0 10 5 Typ. Max. Units ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions2
CL = 50 pF
CL = 50 pF, RL = 1 K (Note 1)
10 Acknowledgement delay time. From CS low to RDY high: Registers Memory 11 Acknowledgement hold time. From CS high to RDY low 12 RDY drive low to HiZ
Note 1: Note 2:
CL = 50 pF CL = 50 pF CL = 50 pF, RL = 1 K (Note 1)
High impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L . A delay of 500 s to 2 ms (Section 14.2 on page 32) must be applied before the first microprocessor access is performed after the RESET pin is set high.
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tCSD
CS
tWS tWH
VCT
WR
tRS tRH
VCT
RD
tAS tAH
VALID ADDRESS
VCT
A0-A13
tDS
VCT
tDH
D0-D15
VALID WRITE DATA
VCT
tAKZ
RDY
tAKD tAKH
VCT
Figure 23 - Intel Non-Multiplexed Bus Timing - Write Access
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Zarlink Semiconductor Inc.
ZL50020
AC Electrical Characteristics - JTAG Test Port Timing Characteristic 1 2 3 4 5 6 7 8 9 TCK Clock Period TCK Clock Pulse Width High TCK Clock Pulse Width Low TMS Set-up Time TMS Hold Time TDi Input Set-up Time TDi Input Hold Time TDo Output Delay TRST pulse width Sym. tTCKP tTCKH tTCKL tTMSS tTMSH tTDIS tTDIH tTDOD tTRSTW 200 Min. 100 20 20 10 10 20 60 30 Typ. Max. Units ns ns ns ns ns ns ns ns ns
Data Sheet
Notes
CL = 30 pF
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tTCKL TCK
tTCKH
tTCKP
tTMSS TMS
tTMSH
tTDIS tTDIH TDi tTDOD TDo tTRSTW TRST
Figure 24 - JTAG Test Port Timing Diagram
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Zarlink Semiconductor Inc.
ZL50020
AC Electrical Characteristics - FPi and CKi Timing when CKIN1-0 bits = 00 (16.384 MHz) Characteristic 1 2 3 4 5 6 7 FPi Input Frame Pulse Width FPi Input Frame Pulse Setup Time FPi Input Frame Pulse Hold Time CKi Input Clock Period CKi Input Clock High Time CKi Input Clock Low Time CKi Input Clock Rise/Fall Time Sym. tFPIW tFPIS tFPIH tCKIP tCKIH tCKIL trCKi, tfCKi Min. 40 20 20 55 27 27 61 67 34 34 3 Typ. 61
Data Sheet
Max. Units Notes 115 ns ns ns ns ns ns ns
8 CKi Input Clock Cycle to Cycle Variation tCVC 0 20 ns Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics - FPi and CKi Timing when CKIN1-0 bits = 01 (8.192 MHz) Characteristic 1 2 3 4 5 6 7 FPi Input Frame Pulse Width FPi Input Frame Pulse Setup Time FPi Input Frame Pulse Hold Time CKi Input Clock Period CKi Input Clock High Time CKi Input Clock Low Time CKi Input Clock Rise/Fall Time Sym. tFPIW tFPIS tFPIH tCKIP tCKIH tCKIL trCKi, tfCKi Min. 90 45 45 110 55 55 122 135 69 69 3 Typ. 122 Max. Units Notes 220 ns ns ns ns ns ns ns
8 CKi Input Clock Cycle to Cycle Variation tCVC 0 20 ns Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
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Zarlink Semiconductor Inc.
ZL50020
AC Electrical Characteristics - FPi and CKi Timing when CKIN1-0 bits = 10 (4.096 MHz) Characteristic 1 2 3 4 5 6 7 FPi Input Frame Pulse Width FPi Input Frame Pulse Setup Time FPi Input Frame Pulse Hold Time CKi Input Clock Period CKi Input Clock High Time CKi Input Clock Low Time CKi Input Clock Rise/Fall Time Sym. tFPIW tFPIS tFPIH tCKIP tCKIH tCKIL trCKi, tfCKi Min. 90 110 110 220 110 110 244 270 135 135 3 Typ. 244
Data Sheet
Max. Units Notes 420 ns ns ns ns ns ns ns
8 CKi Input Clock Cycle to Cycle Variation tCVC 0 20 ns Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tFPIW
FPi
tFPIS tFPIH tCKIP tCKIH tCKIL
CKi
trCKI Input Frame Boundary tfCKI
Figure 25 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS)
tFPIW
FPi
tFPIS tFPIH tCKIP tCKIH tCKIL
CKi
trCKI Input Frame Boundary tfCKI
Figure 26 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus)
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Zarlink Semiconductor Inc.
ZL50020
AC Electrical Characteristics - ST-BUS/GCI-Bus Input Timing Characteristic 1 STi Setup Time 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps 2 STi Hold Time 2.048 Mbps 4.096 Mbps 8.192 Mbps 16.384 Mbps tSIH2 tSIH4 tSIH8 tSIH16 8 8 8 8 ns ns ns ns tSIS2 tSIS4 tSIS8 tSIS16 5 5 5 5 ns ns ns ns Sym. Min. Typ. Max. Units
Data Sheet
Test Conditions
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
FPi CKi (16.384 MHz) FPi CKi (8.192 MHz) FPi CKi (4.096 MHz) tSIS2 tSIH2 STi0 - 31 2.048 Mbps
Bit0 Ch31
Bit7 Ch0
Bit6 Ch0
VCT
tSIS4 tSIH4
Bit0 Ch63 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0
STi0 - 31 4.096 Mbps
VCT
tSIS8 tSIH8 STi0 - 31 8.192 Mbps
Bit1 Ch127
Bit0 Ch127
Bit7 Ch0
Bit6 Ch0
Bit5 Ch0
Bit4 Ch0
Bit3 Ch0
Bit2 Ch0
Bit1 Ch0
Bit0 Ch0
VTT VCT
Input Frame Boundary
Figure 27 - ST-BUS Input Timing Diagram when Operated at 2, 4, 8 Mbps
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
FPi CKi (16.384 MHz) tSIS16 tSIH16 STi0 - 31 16.384 Mbps
Bit1 Ch255 Bit0 Ch255 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0 Bit3 Ch0 Bit2 Ch0 Bit1 Ch0 Bit0 Ch0
VTT VCT
Input Frame Boundary
Figure 28 - ST-BUS Input Timing Diagram when Operated at 16 Mbps
FPi CKi (16.384 MHz) FPi CKi (8.192 MHz) FPi CKi (4.096 MHz) tSIS2 tSIH2 STi0 - 31 2.048 Mbps
Bit7 Ch31
Bit0 Ch0
Bit1 Ch0
VCT
tSIS4 tSIH4
Bit7 Ch63 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0
STi0 - 31 4.096 Mbps
VCT
tSIS8 tSIH8 STi0 - 31 8.192 Mbps
Bit6 Ch127
Bit7 Ch127
Bit0 Ch0
Bit1 Ch0
Bit2 Ch0
Bit3 Ch0
Bit4 Ch0
Bit5 Ch0
Bit6 Ch0
Bit7 Ch0
VTT VCT
Input Frame Boundary
Figure 29 - GCI-Bus Input Timing Diagram when Operated at 2, 4, 8 Mbps
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
FPi CKi (16.384 MHz) tSIS16 tSIH16 STi0 - 31 16.384 Mbps
Bit6 Ch255 Bit7 Ch255 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0 Bit4 Ch0 Bit5 Ch0 Bit6 Ch0 Bit7 Ch0
VTT VCT
Input Frame Boundary
Figure 30 - GCI-Bus Input Timing Diagram when Operated at 16 Mbps AC Electrical Characteristics - ST-BUS/GCI-Bus Output Timing Characteristic 1 STio Delay - Active to Active @2.048 Mbps @4.096 Mbps @8.192 Mbps @16.384 Mbps @2.048 Mbps @4.096 Mbps @8.192 Mbps @16.384 Mbps tSOD2 tSOD4 tSOD8 tSOD16 tSOD2 tSOD4 tSOD8 tSOD16 0 0 0 0 -6 -6 -6 -6 6 6 6 6 0 0 0 0 ns ns ns ns ns ns ns ns Sym. Min. Typ. Max. Units Test Conditions CL = 30 pF Multiplied Clock Mode
Divided Clock Mode
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
FPo0 CKo0 (4.096 MHz)
tSOD2 STio0 - 31 2.048 Mbps
Bit0 Ch31 Bit7 Ch0 Bit6 Ch0
VCT
tSOD4 STio0 - 31 4.096 Mbps
Bit0 Ch63 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0
VCT
tSOD8 STio0 - 31 8.192 Mbps
Bit0 Ch127 Bit7 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0 Bit3 Ch0 Bit2 Ch0 Bit1 Ch0 Bit0 Ch0
VCT
tSOD16 STio0 - 31 16.384 Mbps
Bit2 Bit1 Bit0 Bit7 Ch255 Ch255 Ch255 Ch0 Bit6 Ch0 Bit5 Ch0 Bit4 Ch0 Bit3 Ch0 Bit2 Ch0 Bit1 Ch0 Bit0 Ch0 Bit7 Ch1 Bit6 Ch1 Bit5 Ch1 Bit4 Ch1 Bit3 Ch1 Bit2 Ch1 Bit1 Ch1
VCT
Output Frame Boundary
Figure 31 - ST-BUS Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps
FPo0 CKo0 (4.096 MHz) tSOD2 STio0 - 31 2.048 Mbps
Bit7 Ch31 Bit0 Ch0 Bit1 Ch0
VCT
tSOD4 STio0 - 31 4.096 Mbps
Bit7 Ch63 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0
VCT
tSOD8 STio0 - 31 8.192 Mbps
Bit7 Ch127 Bit0 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0 Bit4 Ch0 Bit5 Ch0 Bit6 Ch0 Bit7 Ch0
VCT
tSOD16 STio0 - 31 16.384 Mbps
Bit5 Bit6 Bit7 Bit0 Ch255 Ch255 Ch255 Ch0 Bit1 Ch0 Bit2 Ch0 Bit3 Ch0 Bit4 Ch0 Bit5 Ch0 Bit6 Ch0 Bit7 Ch0 Bit0 Ch1 Bit1 Ch1 Bit2 Ch1 Bit3 Ch1 Bit4 Ch1 Bit5 Ch1 Bit6 Ch1
VCT
Output Frame Boundary
Figure 32 - GCI-Bus Output Timing Diagram when Operated at 2, 4, 8 or 16 Mbps
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Zarlink Semiconductor Inc.
ZL50020
AC Electrical Characteristics - ST-BUS/GCI-Bus Output Tristate Timing Characteristic 1 2 3 STio Delay - Active to High-Z STio Delay - High-Z to Active Output Drive Enable (ODE) Delay - High-Z to Active CKi @ 4.096 MHz CKi @ 8.192 MHz CKi @ 16.384 MHz Sym. tDZ tZD tZD_ODE Min. -3 -8 -3 -8 Typ. Max. 7 0 7 0 77 260 138 77 Units ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions* Multiplied Clock Mode Divided Clock Mode Multiplied Clock Mode Divided Clock Mode Multiplied Clock Mode Divided Clock Mode
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing. Note 1: High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel the time taken to discharge C L.
FPo0
VCT
CKo0 tDZ STio Valid Data tZD STio Tristate
VCT
Tristate
VCT
Valid Data
VCT
Figure 33 - Serial Output and External Control
ODE tZD_ODE STio HiZ Valid Data tDZ_ODE HiZ
VCT
VCT
Figure 34 - Output Drive Enable (ODE)
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Zarlink Semiconductor Inc.
ZL50020
AC Electrical Characteristics - Clock Mode Input/Output Frame Boundary Alignment Characteristic 1 2 Input and Output Frame Offset in Divided Clock Mode Input and Output Frame Offset in Multiplied Clock Mode Sym.
tFBOS tFBOS
Data Sheet
Min. 5 2
Typ.
Max. 13 10
Units ns ns
Notes
Input reference jitter is equal to zero.
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
FPi CKi (16.384 MHz) FPi CKi (8.192 MHz) FPi CKi (4.096 MHz) Input Frame Boundary tFBOS Output Frame Boundary
FPo0 CKo0 (4.096 MHz)
Figure 35 - Input and Output Frame Boundary Offset
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Zarlink Semiconductor Inc.
ZL50020
Data Sheet
tFPW03 FPo0/3 tFODF03 tCKP03 tCKH03 CKo0/3 tfCK03 Output Frame Boundary trCK03 tCKL03 VCT tFODR03 VCT
Figure 36 - FPo0 and CKo0 Timing Diagram
AC Electrical Characteristics - FPo0/CKo0 and FPo3/CKo3 (4.096 MHz) Timing for Divided Clock Mode and Multiplied Clock Mode with Less than 10 ns of Input Cycle to Cycle Variation Characteristic 1 2 3 4 5 6 7 FPo0 Output Pulse Width FPo0 Output Delay from the FPo0 falling edge to the output frame boundary FPo0 Output Delay from the output frame boundary to the FPo0 rising edge CKo0 Output Clock Period CKo0 Output High Time CKo0 Output Low Time CKo0 Output Rise/Fall Time Sym. tFPW03 tFODF03 tFODR03 tCKP03 tCKH03 tCKL03 trCK03, tfCK03 Min. 239 117 117 239 117 117 244 Typ. 244 Max. 249 127 127 249 127 127 5 Units ns ns ns ns ns ns ns
CL = 30 pF CL = 30 pF
Notes
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics - FPo0/CKo0 and FPo3/CKo3 (4.096 MHz) Timing for Multiplied Clock Mode with More than 10 ns of Cycle to Cycle Variation on CKi Characteristic 1 2 3 4 5 6 FPo0 Output Pulse Width FPo0 Output Delay from the FPo0 falling edge to the output frame boundary FPo0 Output Delay from the output frame boundary to the FPo0 rising edge CKo0 Output Clock Period CKo0 Output High Time CKo0 Output Low Time Sym. tFPW03 tFODF03 tFODR03 tCKP03 tCKH03 tCKL03 Min. 218 117 97 218 117 97 244 Typ. 244 Max. 270 127 146 270 127 146 Units ns ns ns ns ns ns
CL = 30 pF CL = 30 pF
Notes
5 ns 7 CKo0 Output Rise/Fall Time trCK03, tfCK03 Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
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Data Sheet
tFPW1 FPo1/3 tFODF1 tCKP1 tCKH1 CKo1/3 tfCK1 Output Frame Boundary trCK1 tCKL1 VCT tFODR1 VCT
Figure 37 - FPo1 and CKo1 Timing Diagram AC Electrical Characteristics - FPo1/CKo1 and FPo3/CKo3 (8.192 MHz) Timing for Divided Clock Mode and Multiplied Clock Mode with Less than 10 ns of Input Cycle to Cycle Variation Characteristic 1 2 3 4 5 6 FPo1 Output Pulse Width FPo1 Output Delay from the FPo1 falling edge to the output frame boundary FPo1 Output Delay from the output frame boundary to the FPo1 rising edge CKo1 Output Clock Period CKo1 Output High Time CKo1 Output Low Time Sym. tFPW13 tFODF13 tFODR13 tCKP13 tCKH13 tCKL13 Min. 117 56 56 117 56 56 122 Typ. 122 Max. 127 66 66 127 66 66 Units ns ns ns ns ns ns
CL = 30 pF CL = 30 pF
Notes
7 CKo1 Output Rise/Fall Time trCK13, tfCK13 5 ns Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing. AC Electrical Characteristics - FPo1/CKo1 and FPo3/CKo3 (8.192 MHz) Timing for Multiplied Clock Mode with More than 10 ns of Cycle to Cycle Variation on CKi Characteristic 1 2 3 4 5 6 FPo1 Output Pulse Width FPo1 Output Delay from the FPo1 falling edge to the output frame boundary FPo1 Output Delay from the output frame boundary to the FPo1 rising edge CKo1 Output Clock Period CKo1 Output High Time CKo1 Output Low Time Sym. tFPW13 tFODF13 tFODR13 tCKP13 tCKH13 tCKL13 Min. 106 56 46 106 46 46 122 Typ. 122 Max. 127 66 66 148 87 66 Units ns ns ns ns ns ns
CL = 30 pF CL = 30 pF
Notes
7 CKo1 Output Rise/Fall Time trCK13, tfCK13 5 ns Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
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Data Sheet
tFPW23 FPo2/3 tFODF23 tCKP23 tCKH23 CKo2/3 tfCK23 Output Frame Boundary trCK23 tCKL23 VCT tFODR23 VCT
Figure 38 - FPo2 and CKo2 Timing Diagram AC Electrical Characteristics - FPo2/CKo2 and FPo3/CKo3 (16.384 MHz) Timing for Divided Clock Mode and Multiplied Clock Mode with Less than 10 ns of Cycle to Cycle Variation on CKi Characteristic 1 2 3 4 5 6 FPo2 Output Pulse Width FPo2 Output Delay from the FPo2 falling edge to the output frame boundary FPo2 Output Delay from the output frame boundary to the FPo1 rising edge CKo2 Output Clock Period CKo2 Output High Time CKo2 Output Low Time Sym. tFPW23 tFODF23 tFODR23 tCKP23 tCKH23 tCKL23 Min. 56 25 25 56 25 25 61 Typ. 61 Max. 66 36 36 66 36 36 Units ns ns ns ns ns ns
CL = 30 pF CL = 30 pF
Notes
7 CKo2 Output Rise/Fall Time trCK23, tfCK23 5 ns Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing. AC Electrical Characteristics - FPo2/CKo2 and FPo3/CKo3 (16.384 MHz) Timing for Multiplied Clock Mode with More than 10 ns of Cycle to Cycle Variation on CKi Characteristic 1 2 3 4 5 6 FPo2 Output Pulse Width FPo2 Output Delay from the FPo2 falling edge to the output frame boundary FPo2 Output Delay from the output frame boundary to the FPo2 rising edge CKo2 Output Clock Period CKo2 Output High Time CKo2 Output Low Time Sym. tFPW23 tFODF23 tFODR23 tCKP2 tCKH23 tCKL23 Min. 56 25 25 47 17 17 61 Typ. 61 Max. 66 36 36 76 43 43 Units ns ns ns ns ns ns
CL = 30 pF CL = 30 pF
Notes
5 ns 7 CKo2 Output Rise/Fall Time trCK23, tfCK23 Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
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Data Sheet
tFPW3 FPo3 tFODF3 tCKP3 tCKH3 CKo3 tfCK3 Output Frame Boundary trCK3 tCKL3 VCT tFODR3 VCT
Figure 39 - FPo3 and CKo3 Timing Diagram AC Electrical Characteristics - FPo3/CKo3 (32.768 MHz) Timing for Divided Clock Mode and Multiplied Clock Mode with Less than 10 ns of Cycle to Cycle Variation on CKi Characteristic 1 2 3 4 5 6 FPo3 Output Pulse Width FPo3 Output Delay from the FPo3 falling edge to the output frame boundary FPo3 Output Delay from the output frame boundary to the FPo3 rising edge CKo3 Output Clock Period CKo3 Output High Time CKo3 Output Low Time Sym. tFPW3 tFODF3 tFODR3 tCKP3 tCKH3 tCKL3 Min. 27 10 12 27 12 12 30.5 Typ. 30.5 Max. 34 18 21 34 19 19 Units ns ns ns ns ns ns
CL = 30 pF CL = 30 pF
Notes
7 CKo3 Output Rise/Fall Time trCK3, tfCK3 5 ns Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing. AC Electrical Characteristics - FPo3/CKo3 (32.768 MHz) Timing for Multiplied Clock Mode with More than 10 ns of Cycle to Cycle Variation on CKi Characteristic 1 2 3 4 5 6 7 FPo3 Output Pulse Width FPo3 Output Delay from the FPo3 falling edge to the output frame boundary FPo3 Output Delay from the output frame boundary to the FPo3 rising edge CKo3 Output Clock Period CKo3 Output High Time CKo3 Output Low Time CKo3 Output Rise/Fall Time Sym. tFPW3 tFODF3 tFODR3 tCKP3 tCKH3 tCKL3 trCK3, tfCK3 Min. 27 12 12 17 5 12 30.5 Typ. 30.5 Max. 34 19 19 44 29 18 5 Units ns ns ns ns ns ns ns
CL = 30 pF CL = 30 pF
Notes
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
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AC Electrical Characteristics - Divided Clock Mode Output Timing Characteristic 1 2 3 CKo0 to CKo1 (8.192 MHz) delay CKo0 to CKo2 (16.384 MHz) delay CKo0 to CKo3 (16.384 MHz/8.192 MHz/4.096 MHz) delay Sym. tC1D tC2D tC3D Min. -1 -1 -2
Data Sheet
Max. 2 3 2
Units ns ns ns
Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics - Multiplied Clock Mode Output Timing Characteristic 1 2 3 CKo0 to CKo1 (8.192 MHz) delay CKo0 to CKo2 (16.384 MHz) delay CKo0 to CKo3 (32.768 MHz/16.384 MHz/8.192 MHz/4.096 MHz) delay Sym. tC1D tC2D tC3D Min. -1 -1 -1 Max. 2 3 3 Units ns ns ns
Characteristics are over recommended operating conditions unless otherwise stated.
tFPD FPo0
VCT
CKo0 (4.096 MHz) tC1D CKo1 (8.192 MHz) CKo2 (16.384 MHz) tC3D CKo3 (32.768 MHz)
VCT
VCT tC2D VCT
VCT
Figure 40 - Output Timing (ST-BUS Format)
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Zarlink Semiconductor Inc.
b
c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
1 214440 26June03
c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
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